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參數資料
| 型號： | W942516CH |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 4M X 4 BANKS X 16 BIT DDR SDRAM |
| 中文描述： | 4米× 4銀行× 16位DDR SDRAM |
| 文件頁數： | 24/47頁 |
| 文件大小： | 2809K |
| 代理商： | W942516CH |
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W942516CH
- 24 -
16. Data Write Enable /Disable Command
(DM = "L/H" or LDM, UDM = "L/H")
During a Write cycle, the DM or LDM, UDM signal functions as Data Mask and can control every
word of the input data. The LDM signal controls DQ0 to DQ7 and UDM signal controls DQ8 to
DQ15.
9.3 Read Operation
Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read
command is issued after t
RCD
from the Bank Activate command, the data is read out sequentially,
synchronized with both edges of DQS (Burst Read operation). The initial read data becomes available
after
CAS
latency from the issuing of the Read command. The
CAS
latency must be set in the Mode
Register at power-up.
When the Precharge Operation is performed on a bank during a Burst Read and operation, the Burst
operation is terminated.
When the Read with Auto Precharge command is issued, the Precharge operation is performed
automatically after the Read cycle, then the bank is switched to the idle state. This command cannot
be interrupted by any other commands. Refer to the diagrams for Read operation.
9.4 Write Operation
Issuing the Write command after t
RCD
from the bank activate command. The input data is latched
sequentially, synchronizing with both edges(rising &falling) of DQS after the Write command (Burst
write operation). The burst length of the Write data (Burst Length) and Addressing Mode must be set
in the Mode Register at power-up.
When the Precharge operation is performed in a bank during a Burst Write operation, the Burst
operation is terminated.
When the Write with Auto Precharge command is issued, the Precharge operation is performed
automatically after the Write cycle, then the bank is switched to the idle state, The Write with Auto
Precharge command cannot be interrupted by any other command for the entire burst data duration.
Refer to the diagrams for Write operation.
9.5 Precharge
There are two Commands, which perform the precharge operation (Bank Precharge and Precharge
All). When the Bank Precharge command is issued to the active bank, the bank is precharged and
then switched to the idle state. The Bank Precharge command can precharge one bank independently
of the other bank and hold the unprecharged bank in the active state. The maximum time each bank
can be held in the active state is specified as t
RAS (max)
. Therefore, each bank must be precharged
within t
RAS(max)
from the bank activate command.
The Precharge All command can be used to precharge all banks simultaneously. Even if banks are
not in the active state, the Precharge All command can still be issued. In this case, the Precharge
operation is performed only for the active bank and the precharge bank is then switched to the idle
state.
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PDF描述 |
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| W946432AD | 512K X 4 BANKS X 32 BITS DDR SDRAM |
| W963A6BBN | 512K WORD X 16 BIT LOW POWER PSEUDO SRAM |
| W963A6BBN70 | 512K WORD X 16 BIT LOW POWER PSEUDO SRAM |
| W963A6BBN70E | 512K WORD X 16 BIT LOW POWER PSEUDO SRAM |
| W963A6BBN70I | 512K WORD X 16 BIT LOW POWER PSEUDO SRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W9425G6DH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:4M X 4 BANKS X 16 BITS DDR SDRAM |
| W9425G6EH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:4 M 】 4 BANKS 】 16 BITS DDR SDRAM |
| W9425G6EH_0812 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:4 M × 4 BANKS × 16 BITS DDR SDRAM |
| W9425G6EH-5 | 功能描述:IC DDR-400 SDRAM 256MB 66TSSOPII RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應商設備封裝:8-MFP 包裝:帶卷 (TR) |
| W9425G6EH-5I | 制造商:Winbond Electronics Corp 功能描述: |
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