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參數(shù)資料
| 型號(hào)： | W53342 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 60" Voice/Melody/LCD Controller(60”話音/音樂/LCD控制器) |
| 中文描述： | 4-BIT, MROM, MICROCONTROLLER |
| 文件頁數(shù)： | 13/65頁 |
| 文件大小： | 719K |
| 代理商： | W53342 |
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W53322/W53342
Publication Release Date: March 1999
- 13 -
Revision A2
( 0)
System Clock
Generator
T1
T2
T3
T4
Main Oscillator
XIN
XOUT
Sub-oscillator
X32I
X32O
Fosc
Fm
Fs
SCR.1
(FMEN)
HOLD
SCR.0
(F32IN)
LCD Frequency
Selector
F
LCD
Divider
INT0
HCF.0
SCR.3
(DIV5MS)
SCR.2
(FMRCB)
(Fosc= Fs while initial reset)
( 1)
type select
enable
Figure 4. The Dual Clock Operation Mode Control Diagram
System Control Register (SCR with SR=2BH)
The SCR register is organized as 4 bit register SCR.3~SCR.0. Tha function of bit assignment is shown as following.
0
1
2
3
SCR
FMEN
DIV5MB
F32IN =0: F
M
is used as F
OSC
input
=1: F
S
is used as F
OSC
input
FMEN =0: F
M
oscillation is disable
=1: F
M
oscillation is enable
FMRCB =0: F
M
type is RC oscillation
=1: F
M
type is XTAL oscillation
DIV5MB =0 : Divider per 0.5sec will be overflow periodically
=1: Divider per 0.125sec will be overflow periodically.
All bit are possible to read/write, set/clear by user. At initial reset, the SCR is 0001B.
FMRCB
F32IN
Divider
There is one divider as 14-bit/12bit binary up-counter designed to generate periodic interrupts. The divider is incremented
by each clock (Fs). When an overflow is occurred, the divider event flag is set to 1 (EVF.0 = 1). The interrupt is executed
if the divider interrupt enable flag has been set (IEF.0 = 1), or the hold state is terminated if the hold release enable flag
has been set (HEF.0 = 1). There are two time periods (500mS & 125 mS) that can be selected by DIV5MB bit. When
DIV5MB is reset to 0 (default), the 500 mS period time is selected; others DIV5MB is set to 1 to select 125 mS.
Watchdog Timer (WDT)
The watchdog timer (WDT) is used to prevent the program from unknown errors. The WDT function can be enable by
mask option and the clock source is Fosc/1024 or Fosc/16384 by WDTCK (bit 3 of MR1 special register) . At initial reset,
the WDTCK is come from F
OSC
/1024. The WDT overflows is occurred while chip operation is not under control and will
be reset. The contents of the WDT can be reset by the instruction CLR FLAG1, #0010B (CLR WDT). The input clock of
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