
W53322/W53342
Publication Release Date: March 1999
- 17 -
Revision A2
= 1 The internal Timer0 clock rate is Fo
SC
/1024
WDTCK= 0 The watchdog timer clock rate is Fosc/1K
= 1 The watchdog timer clock rate is Fo
SC
/16K
User can read/write and set/clear all bits. At initial reset, MR1 is 0000B.
C
C
#
D
D
#
B
G
G
A
F
F
E
A
#
#
#
E
N
O
T
TM1 preset value
& MFP frequency
3
4
5
261.63
277.18
293.66
311.13
329.63
349.23
369.99
392.00
415.30
440.00
466.16
493.88
523.25
554.37
587.33
622.25
659.26
698.46
739.99
783.99
830.61
880.00
932.23
987.77
260.06
277.69
292.57
309.13
327.68
372.36
390.09
420.10
443.81
442.81
3EH
3AH
37H
34H
31H
2EH
2BH
29H
26H
22H
24H
20H
468.11
496.48
1EH
1CH
1BH
19H
18H
16H
15H
14H
13H
12H
11H
10H
528.51
564.96
585.14
630.15
655.36
712.34
744.72
780.19
819.20
862.84
910.22
963.76
130.81
138.59
146.83
155.56
164.81
174.61
185.00
196.00
207.65
220.00
233.08
246.94
7CH
75H
6FH
68H
62H
5DH
58H
53H
4EH
45H
49H
41H
131.07
138.84
146.28
156.03
165.49
174.30
184.09
195.04
207.39
221.40
234.05
248.24
Tone
frequency
Tone
frequency
TM1 preset value
& MFP frequency
Tone
frequency
TM1 preset value
& MFP frequency
Table 3: TONE output with central tone A4(440HZ)
Mode Register 3 (MR3 with SR=27H)
Mode Register 3 is organized as a 4-bit binary register (MR3.3 to MR3.0) . The bit descriptions are as following: (Initial
value=0000B)
0
1
2
3
MR3
FsENB
V
LCD
P1
P0
V
LCD
= 0 Use internal LCD supplying voltage generated by pump circuit.
= 1 Use external LCD supplying voltage.
FsENB = 0 Enable 32768 Hz crystal
=1 Disable 32768 Hz crystal
P1 = PWM volumn control bit 1
P0 = PWM volumn control bit 0
Note that any one pin of RC port in low state will force the bit MR3.2 low. It means once any one pin of RC port in low
state, the setting action for this bit is invalid.
Interrupts
The W533X2 provides five internal interrupt sources (Divider, TM0, SPEECH, MELODY and TM1) and two external
interrupt source (port RC and port RD). Vector addresses for each of the interrupts are located in the range of program
memory (ROM) addresses 004H to 020H. The flags IEF, PEF, and EVF are used to control the interrupts. When EVF is
set to "1" by hardware and the corresponding bits of IEF and PEF have been set by software, an interrupt is generated.
When an interrupt occurs, all of the interrupts are inhibited until the
EN INT
or MOV IEF,#I instruction is invoked. The