
W53322/W53342
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Auto-reload buffer
8 bits
MR1.1
(TM1SR)
MR0.2
(TM1EN)
Enable
(1)
Underflow signal
EVF.7
1. Reset
2. INT7 accept
3. CLR EVF, #80H
4. Set TM1EN
RE3/TONE
output pin
TONE
MR0.0
(TONE)
8-Bit Binary
Down Counter
(Timer 1)
2
circuit
Reset
Reset
D(0)
MR1.0
(TM1CK)
S
R
Q
T
F
1. MOV TM1L, R or MOV TM1H, R
2. Reset TM1EN
4
4
MOV TM1H,R MOV TM1L,R
Set TM1EN to 1
PORTE.3
32768/4 Hz clock
(1)
Fosc/64
Fosc
(0)
(1)
(0)
(1)
(0)
Figure 7. Organization of Timer 1
For example, when F
T
equals 32768 Hz, depending on the preset value of TM1, the RE3/TONE pin will output a single
tone signal in the tone frequency range from 64 Hz to 16384 Hz. The relation between the tone frequency and the preset
value of TM1 is shown in the Table 3.
Mode Register 0 (MR0 with SR=28H)
Mode Register 0 is organized as a 4-bit binary register (MR0.0 to MR0.3) . The bit descriptions are as following: (Initial
value=0000B)
0
1
2
3
MR0
TONE = 0 RE3 as the data output of PORTE.3.
= 1 RE3 will be as TONE signal output generated from Timer 1
LCDEN =0 LCD display OFF
=1 LCD display ON
TM1EN =0 Timer 1 counting is disable
=1 Timer 1 counting is enable
TM0EN=0 Timer 0 counting is disable
=1 Timer 0 counting is enable
User can read/write and set/clear all bits. At initial reset, MR0 is 0000B.
Mode 1 Register (MR1 with SR=29H)
Mode Register 1 is organized as a 4-bit binary register (MR1.0 to MR1.3) . The bit descriptions are as following: (Initial
value=0000B)
0
1
2
3
MR1
TM1EN
TM0EN
LCDEN
TONE
TM0CK
WDTCK
TM1SR TM1CK
TM1CK= 0 The internal Timer 1 clock rate is F
OSC
.
= 1 The internal Timer1 clock rate is F
OSC
/64.
TM1SR=0 The Timer 1 with internal clock source (depened on TM1CK)
=1 The Timer 1 with sub-frequency/4 (32768/4) clock source
TM0CK= 0 The internal Timer 0 clock rate is Fosc/4