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參數資料
| 型號： | W53342 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 60" Voice/Melody/LCD Controller(60”話音/音樂/LCD控制器) |
| 中文描述： | 4-BIT, MROM, MICROCONTROLLER |
| 文件頁數： | 18/65頁 |
| 文件大小： | 719K |
| 代理商： | W53342 |
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W53322/W53342
- 18 -
interrupts can also be disabled by executing the
DIS INT
instruction. When an interrupt is generated in hold mode, the
hold mode will be released momentarily and interrupt subroutine will be executed. After the RTN instruction is executed in
an interrupt subroutine, the
μ
C will enter hold mode again. The control circuit diagram and operation flow chart are shown
in Figure 8, and Figure 9 separately.
Mode Register 2 (MR2 with SR=26H)
Mode Register 2 is organized as a 1-bit only register . This INTEN bit uses to disable/enable interrupt function.
Instruction of DIS EN uses to reset INTEN bit logic 0, and EN INT set INTEN bit to 1.
0
1
2
3
MR2
X
X
X
INTEN
INTEN = 0 Disable any interrupt process.
= 1 Enable interrupt process which IEF.n is set by 1.
X means do't care.
User can read/write and set/clear INTEN. At initial reset, MR2 is 0001B.
Interrupt Enable Flag Register (IEF with SRP=07H)
The interrupt enable flag is organized as a 8-bit binary register (IEF.0 to IEF.7) that IEFL and IEFH registers store
IEF.0~IEF.3 and IEF.4~IEF.7 separately. These bits are used to control the interrupt conditions. It is controlled by the
MOV IEF, #I instruction with 8 bit immediate data. Of course, MOV IEFH, #I and MOV IEFL, #I instructions can be used
with 4 bit immediate data. When one of these interrupts is accepted, the corresponding to the bit of the event flag will be
reset by hardware, but the other bits are unaffected. In interrupt subroutine, these interrupts will be disable till the
instruction MOV IEF, #I
or EN INT
is executed again. Therefore, to enable these interrupts, the instructions MOV IEF, #I or
EN INT must be executed again. Otherwise, these interrupts can be disable by executing DIS INT instruction. The bit
descriptions are as follows:
2
3
IEF
Speech
X
TM1
RC
RD
Melody
0
1
7
6
5
4
IEFH
IEFL
DIV
TM0
IEF.0 = 1 Interrupt 0 is accepted by overflow from the Divider
IEF.1 = 1 Interrupt 1 is accepted by underflow from the Timer 0.
IEF.2 = 1 Interrupt 2 is accepted by a signal change on port RC.
IEF.3 = 1 Interrupt 3 is accepted by a signal change on port RD
IEF.4 Reserved
IEF.5 = 1 Interrupt 5 is accepted by speech play ending with SPC_busy falling edge
IEF.6 = 1 Interrupt 6 is accepted by melody play ending with MLD_busy falling edge
IEF.7 = 1 Interrupt 7 is accepted by underflow from Timer 1.
All bits can be read/write and set/clear by user.
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| W536060A | VOICE/ MELODY / LCD CONTROLLER |
| W536090A | VOICE/ MELODY / LCD CONTROLLER |
| W536030P | VOICE & MELODY CONTROLLER |
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