
W53322/W53342
Publication Release Date: March 1999
- 25 -
Revision A2
PEF.5 =1 : State change on pin RD1 to release hold mode or perform interrupt
PEF.6 =1 : State change on pin RD2 to release hold mode or perform interrupt
PEF.7 =1 : State change on pin RD3 to release hold mode or perform interrupt
All bit can be read/write and set/clear by user.
Port Status Register 0 and 1 (PSR0, PSR1 with 34H, 35H)
Port status register 0 and 1 are organized as 4-bit binary PSR0.0 to PSR0.3 and PSR1.0 to PSR1.3. PSR0 ( PSR1) will
have the chance to be set to "1" if the PEF.n is enable and RCn (RDn) input state is changed. Then hold mode or
interupt will be occurred. Refer to Figure 10. PSR0 (PSR1) can be read or cleared by the MOVA R, PSR0 (MOVA
R, PSR0 ), and CLR PSR0(CLR PSR0) instructions. The bit descriptions are as follows:
0
1
2
3
PSR0
RC1EG
RC3EG RC2EG
RC0EG
Bit 0 = 1 : RC0 input signal state is changed
= 0 : RC0 input signal state isn't changed
Bit 1 = 1 : RC1 input signal state is changed
= 0 : RC1 input signal state isn't changed
Bit 2 = 1 : RC2 input signal state is changed
= 0 : RC2 input signal state isn't changed
Bit 3 = 1 : RC3 input signal state is changed
= 0 : RC3 input signal state isn't changed
All bit can be read only, and clear 4bit simultaneously.
At initial reset , PSR1 is 0000B
0
1
2
3
PSR1
RD1EG
RD3EG RD2EG
RD0EG
Bit 0 = 1 : RD0 input signal state is changed
= 0 : RD0 input signal state isn't changed
Bit 1 = 1 : RD1 input signal state is changed
= 0 : RD1 input signal state isn't changed
Bit 2 = 1 : RD2 input signal state is changed
= 0 : RD2 input signal state isn't changed
Bit 3 = 1 : RD3 input signal state is changed
= 0 : RD3 input signal state isn't changed
All bit can be read only, and clear 4bit simultaneously.
At initial reset , PSR1 is 0000B
Port C Register (PORTC with SR=3AH)
This register stores the port RC current input state by MOV R, PORTC instructions.
0
1
2
3
PORTC
PC2
PC3
PC1
PC0