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參數資料
| 型號： | W53342 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 60" Voice/Melody/LCD Controller(60”話音/音樂/LCD控制器) |
| 中文描述： | 4-BIT, MROM, MICROCONTROLLER |
| 文件頁數： | 21/65頁 |
| 文件大小： | 719K |
| 代理商： | W53342 |
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W53322/W53342
Publication Release Date: March 1999
- 21 -
Revision A2
EVF.4 ~ EVF.7 separately. It is set by hardware and reset by CLR EVFL,#I and MOV EVFH,#I instruction or the
occurrence of an interrupt. The bit descriptions are as follows:
1
2
3
7
6
5
4
0
Speech
EVFH
EVFL
X
TM1
RC
RD
DIV
TM0
Melody
EVF.0 = 1 Overflow from Divider occurred.
EVF.1 = 1 Underflow from Timer 0 occurred.
EVF.2 = 1 Statel change on port RC occurred.
EVF.3 = 1 State change on port RD occurred.
EVF.4 Reserved
EVF.5 = 1 Speech play ending with SPC_busy flag falling edge occurred.
EVF.6 = 1 Speech play ending with SPC_busy flag falling edge occurred.
EVF.7 = 1 Underflow from Timer 1 occurred.
All bits can be read and clear only by user.
Hold Mode Release Enable Flag Register (HEF with SRP=06H)
The hold mode release enable flag is organized as an 8-bit binary register (HEF.0 to HEF.7) that HEFL and HEFH register
store HEF.0~HEF.3 and HEF.4~ HEF.7 separately. The HEF is used to control the hold mode release conditions. It is
controlled by the MOV HEF, #I instruction with 8 bit immediate data , or MOV HEFH,#I and MOV HEFL,#I with 4 bit
immediate data.. The bit descriptions are as follows:
0
1
2
3
HEF
Speech
7
6
5
4
HEFH
HEFL
X
TM1
RC
RD
DIV
TM0
Melody
HEF.0 = 1 Overflow from the Divider causes hold mode to be released.
HEF.1 = 1 Underflow from Timer 0 causes hold mode to be released.
HEF.2 = 1 Statel change on port RC causes hold mode to be released.
HEF.3 =1 Statel change on port RD causes hold mode to be released
HEF.5 = 1 Speech play ending with SPC_busy flag falling edge causes hold mode to be released
HEF.6 =1 Melody play ending with MLD_busy flag falling edge causes hold mode to be released
HEF.7 = 1 Underflow from Timer 1 causes hold mode to be released.
All bits can be read/write and set/clear by user
Hold mode release Condition Flag Register (HCFL, HCFH with SR=10H & 11H )
The hold mode release condition flag is organized as a 8-bit binary register (HCF0 to HCF7) that HCFL and HCFH
registers store HCF.0~HCF.3 and HCF.4~HCF.7 separately. The hold mode has been released, and is loaded by
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