
W53322/W53342
- 28 -
volume.
FLAG0 Register (FLAG0 with SR=22H)
FLAG0 is organized as a 4-bit register and used to control the speech and melody synthesizers. FLAG0.1~0 are
read/write and set/clear by user., but FLAG0.3 ~ FLAG0.2 are set/clear by chip hardware. At initial reset, FLAG0 is
0000B. The bit description are as following.
0
1
2
3
FLAG0
MLD_busy SPC_busy MLD_play
SPC_play
SPC_paly =0 : Speech play is disable
=1 : Speech play is enable.
MLD_paly =0 : Melody play is disbale.
=1 : Melody play is enable.
SPC_busy =0 : Speech play is finished
=1 : Speech play is processing
MLD_busy =0 : Melody play is finished.
=1 : melody play is processing
SPEECH Function
There are 1.4M bits dedicated speech ROM for speech synthesizer, and can be sepatated as 255 sections different voice
maximun by WINBOND ADPCM power speech coding system. Uc needs to write play section number in SPCH, SPCL ,
and set SPC_play option bit to "1" (bit 0 of FLAG0 special register) to play speech voice . Then SPC_busy bit (bit 2 of
FLAG0) will be changed from low to high and keeps high till speech play is ending. If interrupt flag or hold mode flag
IEF.5, HEF.5, HCF.5 are set, interrupt or hold mode release will be processed while SPC_busy falling edge occurred. The
circuit structure is shown in Figure 12. SPC_play bit can be set to "1" again, after section number had been finished
parallel to serial of previous SPC_play edge. There are minimun 8 instruction delay of two continuous SPC_play rising
shown in Figure 12.
Two LED output with 3HZ frequency can be used to drive external LED during speech playing. The SPCH, SPCL will be
latched during SPC_play risng edge. The speech synthesizer is disabled when MLD_busy bit (bit 3 of FLAG0) is 1, and
so is the melody synthesizer when SPC_busy bit is 1.
The SPC_play is set to 1 to activate the speech synthesizer. The speech synthesizer receives the rising edge of
SPC_play then plays the voice section pointed by SPC.7~SPC.0 and pull the voltage level of SPC_busy to logic 1. The
SPC_busy is cleared by hardware when:
1. the speech synthesizer finishes its tasks and executes an END command;
2.the speech synthesizer receives a rising edge of SPC_play again and the content of SPC.7~SPC.0 is 00H, which forces
the speech synthesizer into STANDBY mode whether the tasks is finished or not.
D
CK
Q
HEF.5
IEF.5
Hold mode release (HCF.5)
Speech interrupt (INT5)
1. Reset
2. CLR EVFH,#0010B
3.MOV FLAG0,#0001B
EVF.5
Parallel to
serial Interface
MOV SPCL, RL
MOV SPCH, RL
4
4
SPC Register
R
VDD
8
SPC_play
(FLAG0.0 bit)
rising edge
min 8 Tcyc
Section Num.
CLK
W528X
TG3
TG2
TG1