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參數資料
| 型號： | W88111AF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | ATAPI CD-ROM DECODER & CONTROLLER |
| 中文描述： | IDE COMPATIBLE, CD ROM CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數： | 12/64頁 |
| 文件大小： | 466K |
| 代理商： | W88111AF |
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W88111AF/W88112F
Preliminary/Confidential
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Publication Release Date: Aug, 1996
Preliminary/ Confidential Revision A0.1
- 12 -
REGISTERS DESCRIPTION
IR - Index Register (read/write)
When URS(pin 32) is low, the Index Register can be accessed by the microprocessor. The value in
IR specifies which internal register to be accessed by microprocessor when URS(pin 32) is high. Note
that the 4 least significant bits of IR will increase following each read or write to any register except
for PFAR(00h). Since IR does not automatically increase from 00h to 01h, consecutive reads to
address 00h will repeatedly read register PFAR(00h). This feature accelerates read operation of
ATAPI Command Packet.
PFAR - Packet FIFO Access Register - (read 00h)
While SCoD(20h.2) is high, the ATAPI Command Packet issued from host is received by the 12-byte
Packet FIFO. Flag TENDb(01h.6) is used to check if the Packet FIFO is full. The microprocessor
can read the ATAPI Command Packet by repeatedly read register PFAR(00h). Once the FIFO
becomes empty, the value FFh will be returned if microprocessor read PFAR.
The Packet FIFO can also be used to receive command parameter less than 12 bytes. First, the
control bit SCoD(20h.2) is set high to select the Packet FIFO to be addressed by the ATAPI Data
port. When DRQ(37h.3) changes from 0 to 1, the lower 4 bits of ATBLO(34h) is latched as the FIFO
threshold. Upon the number of bytes in the FIFO reaches the threshold, flag TENDb(01h.6) becomes
active-low and flag FPKT(30h.1) becomes active-high. Once FPKT becomes high, any data writes to
the ATAPI Data port is rejected.
INTCTL - Interrupt Control Register - (write 01h)
Bit 7: PFNEEN - Packet FIFO Not Empty Interrupt Enable
UINTb(pin 36) is activated when PFNEb(01h.7) becomes active-low if this bit is high.
Bit 6: TENDEN - Transfer End Interrupt Enable
UINTb(pin36) is activated when TENDb(01h.6) becomes active-low if this bit is high. TENDEN is
also automatically enabled if the host issues the Packet Command(A0h) while HIIEN(2Eh.7) is
high and drive is selected.
Bit 5: SRIEN - Sector Ready Interrupt Enable
UINTb(pin36) is activated when SRIb(01h.5) becomes active-low if this bit is high.
相關PDF資料 |
PDF描述 |
|---|---|
| W88112F | ATAPI CD-ROM DECODER & CONTROLLER |
| W88113C | ATAPI CD-ROM DECODER & CONTROLLER |
| W88113CD | ATAPI CD-ROM DECODER & CONTROLLER |
| W88113CF | ATAPI CD-ROM DECODER & CONTROLLER |
| W88227F | ATAPI CD-ROM Decoder(支持ATAPI標準的CD-ROM解碼器) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W88112F | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ATAPI CD-ROM DECODER & CONTROLLER |
| W88113C | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ATAPI CD-ROM DECODER & CONTROLLER |
| W88113CD | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ATAPI CD-ROM DECODER & CONTROLLER |
| W88113CF | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ATAPI CD-ROM DECODER & CONTROLLER |
| W88611P | 制造商:WINBOND 制造商全稱:Winbond 功能描述:VCD 4X RF AMP/DIGITAL SERVO & DSP |
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