
W88111AF/W88112F
Preliminary/Confidential
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Publication Release Date: Aug, 1996
Preliminary/ Confidential Revision A0.1
- 46 -
Clears ARST (2Fh.3)
Deactivates pin ARSTb if ARSTEN (2Fh.3) and ARSTS (2Fh.2) are enabled
Deactivates UINTb if ARSTIEN (2Fh.1) is enabled
MISS2 - Miscellaneous Status Register 0 (read 30h)
Bit 7: SRSTD - Soft Reset with DRQ
This bit becomes high if host activates SRST in the ATAPI Device Control Register while DRQ is
high and the drive is selected. This bit is updated each time the SRST changes from 0 to 1.
Bit 6: CMDC - Command Conflict
This bit becomes high if one of the following events occurs while BSY is high:
Host writes any opcode to ATAPI Command Register while drive is selected.
Host writes any opcode to ATAPI Command Register while shadow drive is selected and
SHDRV (3Fh.6) is enabled.
Host writes opcode 90h (Execute Drive Diagnostics) to ATAPI Command Register.
CMDC is updated each time the host writes the ATAPI Command Register.
Bit 5: TDIR - Data Transfer Direction
If TDIR is high when TENDb (01h.6) changes from 1 to 0, the interrupt is caused by completion of
data transfer from external RAM to host. TDIR is low if activation of TENDb (01h.6) is caused by
completion of data transfer from host to the Packet FIFO.
Bit 4: MBTI - Multi-block Transfer Interrupt
This flag indicates the end of each block transfer while the Multi-block transfer is used.
Bit 3: RPINT - RAM Parity Interrupt Flag
This bit becomes high if a parity error has been detected in the external RAM when RPEN (2Ah.3)
is high. RPINT and the interrupt can be cleared by writing any value to register RAMCF (2Ah).
Bit 2: CRST - Chip Reset Flag
This bit is set high by chip reset. The first read of register MISS2 (30h) following the end of the
chip reset clears CRST to 0.