- 您現在的位置：買賣IC網 > PDF目錄363904 > W88111AF (WINBOND ELECTRONICS CORP) ATAPI CD-ROM DECODER & CONTROLLER PDF資料下載
參數資料
| 型號： | W88111AF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | ATAPI CD-ROM DECODER & CONTROLLER |
| 中文描述： | IDE COMPATIBLE, CD ROM CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數： | 17/64頁 |
| 文件大小： | 466K |
| 代理商： | W88111AF |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
W88111AF/W88112F
Preliminary/Confidential
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Publication Release Date: Aug, 1996
Preliminary/ Confidential Revision A0.1
- 17 -
SCBL/SCBH - Subcode Block Register - (read/write 26h/27h)
SCBL/SCBH form a 9-bit register that contains a block number of the latest available subcode data
that can be read by the host. The number in SCBL/SCBH plus 1 points to the RAM block that is
buffering incoming subcode. The number in SCBL/SCBH is increased by one at the end of subcode
block buffering.
DDBL/DDBH - Decoded Data Block Register - (read/write 28h/29h)
DDBL/DDBH form a 9-bit register that contains the number of the latest available decoded data block
after decoder interrupt occurs. This block number should be used to specify TBL/TBH(24h/25h)
before triggering data transfer to the host. This decoded-data-block-number plus 1 points to the
DRAM block that is buffering incoming serial data and increases by one at the end of each data block
buffering.
CTRL0 - Control Register 0 - (write 0Ah)
Bit 7: DECEN - Decoding Logic Enable
Setting this bit high enables the decoding logic.
Bit 5: EDCEN - Error Detect and Correct Enable
Setting this bit high enables the ECC and EDC logic.
Bit 4: ACEN - Automatic Correction Enable
When this bit is set high during MODE 2 ECC, the type of error correction is automatically
determined by the setting of the FORM bit in the subheader byte. When this bit is low during
MODE 2 ECC, the type of error correction is controlled by F2RQ(0Bh.2).
Bit 2: BUFEN - Buffering Enable
Setting this bit high enables incoming DSP data buffering. When this bit is high, the values of
register HEAD0-3(04h-07h) and SUBH0-3(14h-17h) are retrieved from external RAM rather than
from incoming serial data. When BUFEN is low, any setting of QCEN or PCEN is meaningless.
Bit 1: QCEN - Q-codeword Correction Enable
When this bit is high, Q-codeword RSPC correction logic is enabled.
相關PDF資料 |
PDF描述 |
|---|---|
| W88112F | ATAPI CD-ROM DECODER & CONTROLLER |
| W88113C | ATAPI CD-ROM DECODER & CONTROLLER |
| W88113CD | ATAPI CD-ROM DECODER & CONTROLLER |
| W88113CF | ATAPI CD-ROM DECODER & CONTROLLER |
| W88227F | ATAPI CD-ROM Decoder(支持ATAPI標準的CD-ROM解碼器) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W88112F | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ATAPI CD-ROM DECODER & CONTROLLER |
| W88113C | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ATAPI CD-ROM DECODER & CONTROLLER |
| W88113CD | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ATAPI CD-ROM DECODER & CONTROLLER |
| W88113CF | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ATAPI CD-ROM DECODER & CONTROLLER |
| W88611P | 制造商:WINBOND 制造商全稱:Winbond 功能描述:VCD 4X RF AMP/DIGITAL SERVO & DSP |
發布緊急采購，3分鐘左右您將得到回復。