- 您現在的位置：買賣IC網 > PDF目錄363904 > W88111AF (WINBOND ELECTRONICS CORP) ATAPI CD-ROM DECODER & CONTROLLER PDF資料下載
參數資料
| 型號： | W88111AF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | ATAPI CD-ROM DECODER & CONTROLLER |
| 中文描述： | IDE COMPATIBLE, CD ROM CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數： | 45/64頁 |
| 文件大小： | 466K |
| 代理商： | W88111AF |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁當前第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
W88111AF/W88112F
Preliminary/Confidential
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Publication Release Date: Aug, 1996
Preliminary/ Confidential Revision A0.1
- 45 -
BSY(37h.7)
←
1
PDIAGEN (20h.6)
←
0 and disables pin PDIAGb to high-impedance state
CKSTP (19h.7)
←
0
ATAPI Error Register
←
01h
ATAPI Feature Register
←
00h
ATAPI Interrupt Reason Register
←
01h
ATAPI SAM Tag Byte
←
01h
ATAPI Byte Counter Register Low/High
←
00h
ATAPI Drive Select Register
←
00h
Clear ATAPI Status Register except bit BSY and SERVICE
Activates host interrupt to the microprocessor if HIIEN (2Eh.7) is enabled
Bit 4: SHDC - Shadow Command Flag
This bit becomes high when the host writes a command to a non-existent slave drive. Meanwhile,
UINTb becomes low-active if SHIEN (2Eh.2) is enabled. ATAC is de-activated by the following:
Chip reset or host reset
Reading register ATCMD (37h)
Writing 1 to CLRBSY (20h.4)
Bit 3: ARST - ATAPI Soft Reset Flag
This bit becomes high when ATAPI Soft Reset command (opcode 08h) is written to either master
or slave drive. ARST is de-activated by writing any value to register ARSTACK (30h).
Bit 2: RST - Reset Flag
This bit is high when the chip is currently being reset by chip reset, host reset, or firmware reset.
Bit 1: FRST - Firmware Reset Flag
This bit is high if the current or most recent reset was firmware reset. The first read of register
MISS1 (2Fh) following the end of the firmware reset clears FRST to 0.
Bit 0: HRST - Chip reset or host reset Flag
This bit is high if the current or most recent reset was activated by chip reset or host reset. The
BSY flag is set whenever chip reset or host reset is activated. The first read of register MISS1
(2Fh) following the end of the chip reset or host reset clears HRST to 0.
ARSTACK - ATAPI Soft Reset Acknowledge (write 30h)
Writing any value to register ARSTACK triggers the following events:
相關PDF資料 |
PDF描述 |
|---|---|
| W88112F | ATAPI CD-ROM DECODER & CONTROLLER |
| W88113C | ATAPI CD-ROM DECODER & CONTROLLER |
| W88113CD | ATAPI CD-ROM DECODER & CONTROLLER |
| W88113CF | ATAPI CD-ROM DECODER & CONTROLLER |
| W88227F | ATAPI CD-ROM Decoder(支持ATAPI標準的CD-ROM解碼器) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W88112F | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ATAPI CD-ROM DECODER & CONTROLLER |
| W88113C | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ATAPI CD-ROM DECODER & CONTROLLER |
| W88113CD | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ATAPI CD-ROM DECODER & CONTROLLER |
| W88113CF | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ATAPI CD-ROM DECODER & CONTROLLER |
| W88611P | 制造商:WINBOND 制造商全稱:Winbond 功能描述:VCD 4X RF AMP/DIGITAL SERVO & DSP |
發布緊急采購，3分鐘左右您將得到回復。