
W88111AF/W88112F
Preliminary/Confidential
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Publication Release Date: Aug, 1996
Preliminary/ Confidential Revision A0.1
- 51 -
Ring Control Registers - (read/write 50h to 57h)
These eight registers add flexibility to the block control of external memory that is controlled by
RTC[2:0] initially. Once one of these eight registers is set, all eight registers should be set to take full
control of block configuration of the external memory.
DTRBL/DTRBH - Data Transfer Ring Base Register - (read/write 50h/51h)
Data Transfer Ring Base Register and Data Transfer Ring Ceiling Register treat the external memory
as a ring while transferring data to the host. Data Transfer Ring Base Register specifies the base
block number of this ring.
DTRCL/DTRCH - Data Transfer Ring Ceiling Register - (read/write 52h/53h)
Data Transfer Ring Base Register and Data Transfer Ring Ceiling Register treat the external memory
as a ring while transferring data to the host. Data Transfer Ring Base Register specifies the ceiling
block number of this ring. The first block to be transferred is specified by TBL/TBH (24h/25h). The
further data transfer after the end of Data Transfer Ceiling block will access data in Data Transfer
Base block.
WBRBL/WBRBH - Write Buffer Ring Base Register - (read/write 54h/55h)
Write Buffer Ring Base Register and Write Buffer Ring Ceiling Register treat the external memory as
a ring while buffering the serial data from DSP. Write Buffer Ring Base Register specifies the base
block number of this ring.
WBRCL/WBRCH - Write Buffer Ring Ceiling Register - (read/write 56h/57h)
Write Buffer Ring Base Register and Write Buffer Ring Ceiling Register treat the external memory as
a ring while buffering the serial data from DSP. Write Buffer Ring Base Register specifies the base
block number of this ring. The first block to be buffered is specified by DDBL/DDBH(28h/29h).
Further serial data buffering after the end of Write Buffer Ceiling block will buffer serial data into the
Write Buffer Base block.
SCTC - Subcode Timer Control Register - (write 5Ah)
If SBXCK (2Ch.7) and CD2SC (2Ch.5) are both 0, the clock used by subcode logic clock is controlled
by SUBCS[2:0] unless any non-zero value is written into register SCTC (5Ah). The value of register
SCTC should be calculated as follows:
( N + 2 )
×
tc
×
dsf =
11.3 / 2
where
tc
is the internal clock period(ex: 50nS for 20MHz crystal),
dsf
is the disk speed factor(ex: 4 for 4-fold speed drive).