
W88111AF/W88112F
Preliminary/Confidential
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Publication Release Date: Aug, 1996
Preliminary/ Confidential Revision A0.1
- 47 -
Bit 1: FPKT -Full Packet Flag
This bit becomes high if the host has written the number of data bytes indicated in register ATBLO
( less than 12 bytes), or the host has written a 12-byte command packet. If CoD (32h.0) is low
when DRQ (37h.3) changes from 0 to 1, the count in ATBLO is latched as a threshold value for
FPKT logic. If CoD is high when DRQ (37h.3) change from 0 to 1, the threshold value of FPKT
logic is set as 12. Whenever the number of bytes in the Packet FIFO equals the threshold value,
flag FPKT becomes high. To receive data from host using Packet FIFO, CoD (32h.0) and ATBLO
(32h) should be updated before DRQ changes from 0 to 1.
Bit 0: APKT - Automatic Packet Transfer Flag
This bit is set to 1 when host writes opcode A0h to ATA Command Register if drive is selected and
APKTEN (18h.7) has been enabled. When APKT is high, BSY is controlled by the Automatic
Packet Transfer logic. Hence, setting of CLRBSY (20h.4) and SETBSY (20h.4) is of no effect.
APKT is de-activated by writing any value to register TACK(07h). APKT is de-activated by chip
reset or host reset but is not changed by firmware reset.
ATERR - ATAPI Error Register (write 31h)
This register is set as 01h by the following:
Chip reset or host reset
SRST
Execute Drive Diagnostics Command
Triggering SIGT (17h.4)
ATFEA - ATAPI Feature Register (read 31h)
This register is de-activated by the following:
Chip reset or host reset
SRST
Execute Drive Diagnostics Command
Triggering SIGT (17h.4)
ATINT - ATAPI Interrupt Reason Register (read/write 32h)
This register is set as 01h by the following:
Chip reset or host reset
SRST
Execute Drive Diagnostics Command
Triggering SIGT (17h.4)