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參數(shù)資料
| 型號： | W88111AF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | ATAPI CD-ROM DECODER & CONTROLLER |
| 中文描述： | IDE COMPATIBLE, CD ROM CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 30/64頁 |
| 文件大小： | 466K |
| 代理商： | W88111AF |
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W88111AF/W88112F
Preliminary/Confidential
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Publication Release Date: Aug, 1996
Preliminary/ Confidential Revision A0.1
- 30 -
FPKT (30h.1)
←
1
TENDb (01h.6)
←
0
Pin UINTb activate if TENDEN (01h.6) has been enabled
Writing any value to register TACK (07h) deactivates APKT, TENDb, and corresponding interrupt.
Bit 6: ADCEN - Automatic DRQ Clearing Enable
When this bit is high, DRQ (37h.3) is cleared to 0 and BSY (37h.7) is set to 1 after the end of
following transfers:
Host reads from external RAM
Host reads from DF0-DF7
Host writes to Command Packet FIFO
Bit 5: ASCEN - Automatic Status Completion Enable
When this bit is high, Status Completion is performed after the end of the following transfers:
Host reads from external RAM
Host reads from DF0-DF7
Host writes to Command Packet FIFO
ADCEN (18h.6) should be enabled when ASCEN is enabled to provide clearing of DRQ (37h.3)
and setting of BSY (37h.7). If both ADCEN and ASCEN are enabled, the following hardware
sequence is executed at the end of one of the above data transfers:
Set BSY
DRQ (37h.3)
←
0
CHECK (37h.0)
←
ACHECK (3Eh.0)
CORR (37h.2)
←
ACORR (3Eh.2)
DRDY(37h.6)
←
ADRDY (3Eh.6)
ATINT (32h)
←
03h
Clear BSY
HIRQ (2Eh.3)
←
1
APKTEN (18h.7)
←
1, if AUTOEN (18h.4) is high
ASCEN (18h.5)
←
0
After detecting the interrupt, the host reads the ATAPI Status Register and if necessary, the Error
Register for the command completion status.
Bit 4: AUTOEN - Automatic APKTEN Set After Status Completion Enable
When this bit is high, APKTEN (18h.7) will be set after Automatic Status Completion sequence
triggered by either SCT (17h.0) or ASCEN (18h.5).
Bit 3: STBCEN - Set Transfer Byte Count Enable
When this bit is high, the value (TBCL,H+1)
×
2 is loaded into ATBLO and ATBHI when ADTT
(17h.2) is triggered and PIO (1Fh.2) has been set high. STBCEN should not be set for Multiple
Block Transfer. Instead, ATBLO/ATBHI should be set by firmware to: (MBKC+1)
×
(TBCL,H+2).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W88112F | ATAPI CD-ROM DECODER & CONTROLLER |
| W88113C | ATAPI CD-ROM DECODER & CONTROLLER |
| W88113CD | ATAPI CD-ROM DECODER & CONTROLLER |
| W88113CF | ATAPI CD-ROM DECODER & CONTROLLER |
| W88227F | ATAPI CD-ROM Decoder(支持ATAPI標準的CD-ROM解碼器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W88112F | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ATAPI CD-ROM DECODER & CONTROLLER |
| W88113C | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ATAPI CD-ROM DECODER & CONTROLLER |
| W88113CD | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ATAPI CD-ROM DECODER & CONTROLLER |
| W88113CF | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ATAPI CD-ROM DECODER & CONTROLLER |
| W88611P | 制造商:WINBOND 制造商全稱:Winbond 功能描述:VCD 4X RF AMP/DIGITAL SERVO & DSP |
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