
W88111AF/W88112F
Preliminary/Confidential
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Publication Release Date: Aug, 1996
Preliminary/ Confidential Revision A0.1
- 43 -
Bit 1: PDIAGb - Pin PDIAGb Flag
This bit reflects the status of pin PDIAGb.
Bit 0: DASPb - Pin DASPb Flag
This bit reflects the status of pin DASPb.
MISC1 - Miscellaneous Control Register 1 (write 2Fh)
Bit 7: ARRC - ATAPI Register Read Control
When this bit is high, the ATAPI registers can be read regardless of the value of BSY if the drive is
selected.
Bit 6: SARRC - Shadow Drive ATAPI Register Read Control
When this bit is high, the Shadow ATAPI registers can be read regardless of the value of BSY if
the shadow drive is selected.
Bit 5,4: These two bits should be write 0s after power-on.
Bit 3: ARSTEN - ATAPI Soft Reset Pin Enable
When this bit is high, pin ARSTb is enabled as output signal. The timing of pin ARSTb signal is
also controlled by ARSTS (2Fh.2).
Bit 2: ARSTS - Pin ARSTb Timing Select
When this bit is high, pin ARSTb (if enabled) becomes active-low if host writes an ATAPI Soft
Reset Command. Writing any value to register ARSTACK (30h) de-activates pin ARSTb. When
this bit is low, pin ARSTb (if enabled) becomes active-low if host writes an ATAPI Soft Reset
Command and automatically de-activates itself after 256 system clock.
Bit 1: ARSTIEN - ATAPI Soft Reset Interrupt Enable
When this bit is high, pin UINTb becomes active-low whenever host writes an ATAPI Soft Reset
Command.
Bit 0: ARWC - ATAPI Register Write Control
Host writes to ATAPI registers (except Device Control Register) will not take effect when ARWC
and BSY are high, if BSY is not set by the following commands: