
W88111AF/W88112F
Preliminary/Confidential
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Publication Release Date: Aug, 1996
Preliminary/ Confidential Revision A0.1
- 31 -
Bit 1: ABYEN - Automatic BSY Set Enable
When this bit is high, the following sequence is executed when Disk Seek Complete is triggered by
DSCT (17h.5):
Set BSY
DSC (37h.4)
←
1
Clear BSY
DSCT
←
0
Bit 0: A0IEN - A0h Command Interrupt Enable
If this bit is high and APKTEN (18h.7) has been enabled, HIRQ (2Eh.3) becomes active-high after
an opcode A0h is issued to ATA Command Register.
CCTL0 - Clock Control Register 0 - (write 19h)
Bit 7: CKSTP - Clock Stop
Setting this bit high stops the internal clock and the clock output at pin CLKO.
CKSTP is de-activated by the following events:
Chip reset or host reset or firmware reset
Command write from the host while the drive is selected
Host issues Diagnostic Command, regardless of drive selection
Host issues command to shadow drive if SHDRV (3Fh.6) is enabled
Host sets bit SRST in ATAPI Device Control Register high, regardless of drive selection
Bit 6: PJSEL - Parity/Jumper Select
When this pin is high, pin PAR/JP is used as buffer RAM Parity Pin. When this pin is low, the
inverted value of pin PAR/JP is sampled into control bit DRV1b (2Eh.4). The timing of sampling is
controlled by JPSS (19h.5).
Bit 5: JPSS - Jumper Sampling Select
This bit is used to control the sampling of pin PAR/JP if PJSEL (19h.6) is low. When JPSS is
high, pin PAR/JP is sampled while chip reset is active. When this bit is low, PAR/JP is sampled
while chip reset or host reset are active.
Bit 4: Reserved
Bit 3-0: CKS[3:0] - Clock Skew Control
CKS[3:0] are used to control the duty cycle of the internal clock.