
W88111AF/W88112F
Preliminary/Confidential
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Publication Release Date: Aug, 1996
Preliminary/ Confidential Revision A0.1
- 38 -
SUBSTA - Subcode Status Register - (read 22h)
Bits 7-3: Reserved
Bit 2: MSS - Missing Subcode Sync
A missing-subcode-sync sets MSS high and negates SCIb (01h.0). A microprocessor interrupt is
also activated if SCIEN (2Ch.4) is enabled.
Bit 1: NESBK - Normal End of Subcode Block
A normal-subcode-block-end sets NESBK high and negates SCIb (01h.0). A microprocessor
interrupt is also activated if SCIEN (2Ch.4) is enabled.
Bit 0: ISS - Illegal Subcode Sync
An illegal-subcode-sync sets ISS high and negates SCIb (01h.0). A microprocessor interrupt is
activated also if SCIEN (2Ch.4) is enabled.
RAMCF - RAM Configuration Register - (read/write 2Ah)
Bit 7: RFTYP - Refresh Type
The refresh mode of DRAM is CAS-before-RAS if this bit is high. The refresh mode of DRAM is
RAS-only if this bit is low.
Bit 6: RFTRG - RAM Filling Trigger
Setting this bit high triggers the DRAM filling. All locations in the external RAM will be filled with
the value in register RAMWR (1Eh). The value (ex:00h) should be written to registers RACL,
RACU, and RACH before triggering RFTRG. RFC (2Ah.5) will change from 0 to 1 when all RAM
locations have been filled. After RAM Filling has completed, the microprocessor should clear
RFTRG to 0.
Bit 5: RFC - RAM Fill Completion Flag (read only)
RFC (2Ah.5) will change from 0 to 1 when all RAM locations have been filled with the value in
register RAMWR (1Eh). RFC will return to 0 when RFTRG is disabled.
Bit 5: RPIEN - RAM Parity Interrupt Enable (write only)
Setting this bit high enables RAM-parity-interrupt to activate pin UINTb.