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參數(shù)資料
| 型號(hào)： | W946432AD |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 512K X 4 BANKS X 32 BITS DDR SDRAM |
| 中文描述： | 為512k × 4銀行× 32位DDR內(nèi)存 |
| 文件頁(yè)數(shù)： | 11/40頁(yè) |
| 文件大小： | 462K |
| 代理商： | W946432AD |
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W946432AD
11
Burst Length
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable,
as shown in Table 1: The burst length determines the maximum number of column locations that can be
accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both
the sequential and the interleaved burst types.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively
selected. All accesses for that burst take place with in this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely selected by A1-A7 when the burst length is set to two,
by A2-A7 when the burst length is set to four and by A3-A7 when the burst length is set to eight. The
remaining address bit is used to select the starting location within the block. The programmed burst length
applies to both READ and WRITE bursts.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to
as the burst type and is selected by bit A3.
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting
column address, as shown in Table 1:.
Table 1:BURST DEFINITION
Starting Column
Address:
A0
0
2
1
A1 A0
0 0
0 1
1 0
1 1
A2 A1 A0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
NOTE:
1. For a burst length of two, A1-A7 selects the two-data-element block; A0 selects
the first access within the block.
2. For a burst length of four, A2-A7 selects the four-data-element block; A0-A1
selects the first access within the block.
3. For a burst length of eight, A3-A7 selects the eight-data- element block; A0-A2
selects the first access within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
Order of Accesses Within a Burst
Type = Sequential
Burst Length
Type = Interleaved
0 - 1
1 – 0
0 - 1
1 – 0
0–1–2-3
1–2–3–0
2–3–0–1
3–0–1–2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
4
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
8
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W963A6BBN | 512K WORD X 16 BIT LOW POWER PSEUDO SRAM |
| W963A6BBN70 | 512K WORD X 16 BIT LOW POWER PSEUDO SRAM |
| W963A6BBN70E | 512K WORD X 16 BIT LOW POWER PSEUDO SRAM |
| W963A6BBN70I | 512K WORD X 16 BIT LOW POWER PSEUDO SRAM |
| W963A6BBN80 | 512K WORD X 16 BIT LOW POWER PSEUDO SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W9464G6IB | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M × 4 BANKS × 16 BITS DDR SDRAM |
| W9464G6IH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M ?? 4 BANKS ?? 16 BITS DDR SDRAM |
| W9464G6JH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M ? 4 BANKS ? 16 BITS DDR SDRAM |
| W9464G6JH-4 | 制造商:Winbond Electronics Corp 功能描述:IC DDR SDRAM 64M 200MHZ 66TSOP |
| W9464G6JH-5 | 制造商:Winbond Electronics Corp 功能描述:64MBIT DDRI 制造商:Winbond Electronics Corp 功能描述:IC DDR SDRAM 64M 200MHZ 66TSOP |
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