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參數資料
型號: W946432AD
廠商: WINBOND ELECTRONICS CORP
英文描述: 512K X 4 BANKS X 32 BITS DDR SDRAM
中文描述: 為512k × 4銀行× 32位DDR內存
文件頁數: 27/40頁
文件大小: 462K
代理商: W946432AD
W946432AD
PRELIMINARY DATE: 9/8/00
27
.
Figure18:WRITE TO PRECHARGE – DQSS, INTERRUPTING
WRITE
NOP
PRE
NOP
NOP
t
WTR
Bank a,
Col b
DI
b
DQ
DM
DQS
ADDRESS
COMMAND
CK
CK
DON'T CARE
WRITE TO PRECHARGE - DQSS, INTERRUPTING
T1
T2
T3
T4
T5
T0
T6
T7
T8
T9
t
DQSS
NOP
Bank
(a or all)
T10
T11
t
RP
*1
*1
*2
DI b = Data In for column b
A interrupted burst of 4 or 8 is shown, 2 data elements are written
1 subsequent element of Data In is applied in the programmed order following DI b
tWTR is referenced from the first postive CK edge after the last desired Data In pair
The PRECHARGE command masks the last two data elements in the burst
A8 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
*1 = can be don't care for programmed burst length of 4
*2 = for programmed burst length of 4, DQS becomes don't care at this point
Figure19:WRITE TO PRECHARGE – DQSS, ODD NUMBER OF DATA, INTERRUPTING
WRITE
NOP
PRE
NOP
NOP
t
WTR
Bank a,
Col b
DI
b
DQ
DM
DQS
ADDRESS
COMMAND
CK
CK
DON'T CARE
WRITE TO PRECHARGE - DQSS, ODD NUMBER OF DATA, INTERRUPTING
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
DQSS
NOP
Bank
(a or all)
T10
T11
t
RP
*1
*1
*2
DI b = Data In for column b
A interrupted burst of 4 or 8 is shown, 1 data element is written
tWTR is referenced from the first postive CK edge after the last desired Data In pair
The PRECHARGE command masks the last two data elements in the burst
A8 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
*1 = can be don't care for programmed burst length of 4
*2 = for programmed burst length of 4, DQS becomes don't care at this point
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W963A6BBN 512K WORD X 16 BIT LOW POWER PSEUDO SRAM
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