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參數資料
| 型號： | W946432AD |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 512K X 4 BANKS X 32 BITS DDR SDRAM |
| 中文描述： | 為512k × 4銀行× 32位DDR內存 |
| 文件頁數： | 3/40頁 |
| 文件大小： | 462K |
| 代理商： | W946432AD |
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W946432AD
PIN DESCRIPTION
PIN NAME
FUNCTION
DESCRIPTION
CLK, CLK
Differential clock
input
All address and control input signals are sampled on the crossing of the positive edge of CLK
and negative edge of CLK . Output (read) data is referenced to the crossings of CLK and
CLK (both directions of crossing).
CKE
Clock Enable
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input
buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and
SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any
bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry.
CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE must be
maintained high throughout READ and WRITE accesses. Input buffers, excluding CLK, CLK
and CKE are disabled during POWER-DOWN. Input buffers, excluding CKE are disabled
during SELF REFRESH.
CS
Chip Select
All commands are masked when CS is registered HIGH. CS provides for external bank
selection on systems with multiple banks. CS is considered part of the command code.
RAS , CAS ,
WE
Command Inputs
RAS , CAS and WE (along with CS ) define the command being entered.
DM
Input Data Mask
DM is an input mask signal for writes data. Input data is masked when DM is sampled HIGH
along with that input data during a WRITE access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ and DQS loading.
BA0, BA1
Bank Address
BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is
being applied.
A0-A10
Address Input
Provide the row address for ACTIVE commands, and the column address and AUTO
PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array
in the respective bank. A8 is sampled during a PRECHARGE command to determine whether
the PRECHARGE applies to one bank (A8 LOW) or all banks (A8 HIGH). If only one bank is
to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-
code during a MODE REGISTER SET command. BA0 and BA1 define which mode register is
loaded during the MODE REGISTER SET command (MRS or EMRS).
DQ
Data Input/Output Data bus
DQS
Data Strobe
Output with read data, input with write data. Edge-aligned with read data, centered in write
data. Used to capture write data.
V
DD
Q
V
SS
Q
V
DD
V
SS
NC
DQ Power
DQ Ground
Supply Power
No Connection
2.5V ± 0.2V.
Ground.
2.5V ± 0.2V
Ground.
No connection
V
REF
SSTL_2 reference voltage.
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相關代理商/技術參數 |
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| W9464G6IB | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M × 4 BANKS × 16 BITS DDR SDRAM |
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| W9464G6JH-4 | 制造商:Winbond Electronics Corp 功能描述:IC DDR SDRAM 64M 200MHZ 66TSOP |
| W9464G6JH-5 | 制造商:Winbond Electronics Corp 功能描述:64MBIT DDRI 制造商:Winbond Electronics Corp 功能描述:IC DDR SDRAM 64M 200MHZ 66TSOP |
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