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參數資料
| 型號： | W946432AD |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 512K X 4 BANKS X 32 BITS DDR SDRAM |
| 中文描述： | 為512k × 4銀行× 32位DDR內存 |
| 文件頁數： | 9/40頁 |
| 文件大小： | 462K |
| 代理商： | W946432AD |
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W946432AD
9
FUNCTIONAL DESCRIPTION
The W946432AD is a high speed CMOS, dynamic random access memory containing 67,108,864 bits. The
W946432AD is internally configured as a quad bank DRAM.
The W946432AD uses a double data rate architecture to achieve high speed operation. The double data rate
architecture is essentially a 32 prefetch architecture, with an interface designed to transfer two data words
per clock cycle at the I/O pins. A single read or write access for the W946432AD consists of a single 32bit
wide, one clock cycle data transfer at the internal DRAM core and two corresponding 32bit wide, one half
clock cycle data transfers at the I/O pins.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed
(BA0, BA1 select the bank; A0-A10 select the row). The address bits registered coincident with the READ or
WRITE command are used to select the starting column location for the burst access.
Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide etailed
information covering device initialization, register definition, command descriptions and device operation.
INITIALIZATION
W986432AD must be powered up and initialized in a predefined manner. Operational procedures other than
those specified may result in undefined operation.
Power must first be applied to V
DD
, then to V
DD
Q, and
finally to V
REF
(and to the system V
TT
). V
TT
must be applied after V
DD
Q to avoid device latch up, which may
cause permanent damage to the device. V
REF
can be applied any time after V
DD
Q, but is expected to be
nominally coincident with V
TT
. Except for CKE, inputs are not recognized as valid until after V
REF
is applied.
CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after V
DD
is applied. Maintaining an
LVCMOS LOW level on CKE during power up is required to guarantee that the DQ and DQS outputs will be
in the High-
Z
state, where they will remain until driven in normal operation (by a read access).
After all power
supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200μs delay
prior to applying an executable command.
Once the 200μs delay has been satisfied, a DESELECT or NOP command should be applied, and CKE
should be brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied.
Next a MODE REGISTER SET command should be issued for the Extended Mode Register, to enable the
DLL, then a MODE REGISTER SET command should be issued for the Mode Register, to reset the DLL,
and to program the operating parameters. 200 clock cycles are required between the DLL reset and any read
command. A PRECHARGE ALL command should be applied, placing the device in the “all banks idle” state.
Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER
SET command for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating
parameters without resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready
for normal operation.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| W9464G6IB | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M × 4 BANKS × 16 BITS DDR SDRAM |
| W9464G6IH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M ?? 4 BANKS ?? 16 BITS DDR SDRAM |
| W9464G6JH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M ? 4 BANKS ? 16 BITS DDR SDRAM |
| W9464G6JH-4 | 制造商:Winbond Electronics Corp 功能描述:IC DDR SDRAM 64M 200MHZ 66TSOP |
| W9464G6JH-5 | 制造商:Winbond Electronics Corp 功能描述:64MBIT DDRI 制造商:Winbond Electronics Corp 功能描述:IC DDR SDRAM 64M 200MHZ 66TSOP |
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