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參數資料
| 型號： | W946432AD |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 512K X 4 BANKS X 32 BITS DDR SDRAM |
| 中文描述： | 為512k × 4銀行× 32位DDR內存 |
| 文件頁數： | 17/40頁 |
| 文件大小： | 462K |
| 代理商： | W946432AD |
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W946432AD
PRELIMINARY DATE: 9/8/00
17
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To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute
refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given
DDR SDRAM, meaning that the maximum absolute interval between any AUTO REFRESH command and
the next AUTO REFRESH command is 9 * 15.6us (140.4us). This maximum absolute interval is short
enough to allow for DLL updates internal to the DDR SDRAM to be restricted to AUTO REFRESH cycles,
without allowing too much drift in tAC between updates.
SELF REFRESH
The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the
system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external
clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is
disabled (LOW). The DLL is automatically disabled upon entering SELF REFRESH, and is automatically
enabled upon exiting SELF REFRESH (200 clock cycles must then occur before a READ command can be
issued). Input signals except CKE are “Don’t Care” during SELF REFRESH.
The procedure for exiting self refresh requires a sequence of commands. First, CK must be stable prior to
CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP commands issued for tXSNR
because time is required for the completion of any internal refresh in progress. A simple algorithm for
meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other
command.
OPERATIONS
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued to a bank within the DDR SDRAM, a row in that bank
must be “opened.” This is accomplished by the ACTIVE command, which selects both the bank and the row
to be activated.
The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A10 selects the
row. The maximum time that each bank can be held in the active state is specified as tRAS (max). After this
command is issued, Read or Write operation can be executed.
After opening a row, a READ or WRITE command may be issued to that row, subject to the tRCD
specification.
A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous
active row has been “closed” (precharged). The minimum time interval between successive ACTIVE
commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which
results in a reduction of total row access overhead. The minimum time interval between successive ACTIVE
commands to different banks is defined by tRRD.
相關PDF資料 |
PDF描述 |
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| W963A6BBN | 512K WORD X 16 BIT LOW POWER PSEUDO SRAM |
| W963A6BBN70 | 512K WORD X 16 BIT LOW POWER PSEUDO SRAM |
| W963A6BBN70E | 512K WORD X 16 BIT LOW POWER PSEUDO SRAM |
| W963A6BBN70I | 512K WORD X 16 BIT LOW POWER PSEUDO SRAM |
| W963A6BBN80 | 512K WORD X 16 BIT LOW POWER PSEUDO SRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W9464G6IB | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M × 4 BANKS × 16 BITS DDR SDRAM |
| W9464G6IH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M ?? 4 BANKS ?? 16 BITS DDR SDRAM |
| W9464G6JH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M ? 4 BANKS ? 16 BITS DDR SDRAM |
| W9464G6JH-4 | 制造商:Winbond Electronics Corp 功能描述:IC DDR SDRAM 64M 200MHZ 66TSOP |
| W9464G6JH-5 | 制造商:Winbond Electronics Corp 功能描述:64MBIT DDRI 制造商:Winbond Electronics Corp 功能描述:IC DDR SDRAM 64M 200MHZ 66TSOP |
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