
28229-DSH-001-B
Mindspeed Technologies
2
-7
CX28224/5/9 Data Sheet
CX2822x Hardware Description
M
ic
ro
In
terf
ac
e
MAS*, MWr*
Microprocessor
Address Strobe
A1
I
When MSyncMode is asserted high, this pin is an address
strobe pin. When the MAS* pin is asserted low, it indicates
a valid address, MicroAddr[10:0]. This signal is used to
qualify read and write accesses.
When MSyncMode is asserted low, this pin is a write
control pin. When MWr* is asserted low, a write access is
enabled and the MicroData[7:0] pin values will be written
to the memory location indicated by the MicroAddr[10:0]
pins. The write access assumes the device is chip selected
(MCS* = 0), a read access is not being requested (MRd* =
1), and the device is not being reset (Reset* = 1).
MicroAddr[0]
Microprocessor
Address Bus
B1
I
These 11 bits are an address input for identifying the
register to access.
MicroAddr[1]
C2
MicroAddr[2]
E4
MicroAddr[3]
D2
MicroAddr[4]
C1
MicroAddr[5]
D1
MicroAddr[6]
E3
MicroAddr[7]
F4
MicroAddr[8]
E2
MicroAddr[9]
E1
MicroAddr[10]
M4
MicroData[0]
Microprocessor Data
Bus
N3
I/O
A bi-directional data bus for reading and writing data to
internal registers.
MicroData[1]
N4
MicroData[2]
N1
MicroData[3]
N2
MicroData[4]
P2
MicroData[5]
P1
MicroData[6]
R1
MicroData[7]
R2
MicroInt*
Microprocessor
Interrupt Request
T1
O
When active low, the device needs servicing. It remains
active until the pending interrupt is processed by the
Interrupt Service Routine. This pin is an open drain output
for an external wired OR logic implementation. An external
pull-up resistor is required for this pin.
Table 2-3. CX2822x Pin Descriptions (2 of 12)
Pin Label
Signal Name
No.
I/O
Description