
7-4
Mindspeed Technologies
28229-DSH-001-B
Registers
CX28224/5/9 Data Sheet
Table 7-4 lists several registers used for CX2822x’s basic functions, including device-
and port-level operating modes.
Table 7-5 lists the control registers used for transmission of traffic.
0x31
IDLCNTM
R
(2)
Idle Cell Receive Counter (middle byte)
0x32
IDLCNTH
R
(2)
Idle Cell Receive Counter (high byte)
0x33
LOCDCNT
R
(2)
LOCD Event Counter
0x34
TXCNTL
R
(2)
Transmitted Cell Counter (low byte)
0x35
TXCNTM
R
(2)
Transmitted Cell Counter (mid byte)
0x36
TXCNTH
R
(2)
Transmitted Cell Counter (high byte)
0x37
CORRCNT
R
(2)
Corrected HEC Error Counter
0x38
RXCNTL
R
(2)
Received Cell Counter (low byte)
0x39
RXCNTM
R
(2)
Received Cell Counter (mid byte)
0x3A
RXCNTH
R
(2)
Received Cell Counter (high byte)
0x3B
UNCCNT
R
(2)
Uncorrected HEC Error Counter
0x3C
NONCNTL
R
(2)
Non-Matching Cell Counter (low byte)
0x3D
NONCNTH
R
(2)
Non-Matching Cell Counter (high byte)
0x3E
—
——
Reserved, set to a logical 0
—
0x3F
—
——
Reserved, set to a logical 0
—
FOOTNOTE:
(1) One-second latching is enabled by setting EnStatLat (bit 5) in the MODE register (0x0202) to a logical 1.
(2) One-second latching is enabled by setting EnCntrLat (bit 4) in the MODE register (0x0202) to a logical 1.
Table 7-4. General Use Registers
Port Offset
Address
Name
Description
Page
Number
0x200
MODE
Device Mode Control Register
0x04
PMODE
Port Mode Control Register
0x05
IOMODE
Input/Output Mode Control Register
0x203
OUTSTAT
Output Pin Control Register
Table 7-3. Port Control and Status Registers (3 of 3)
Port Offset
Address
Name
Type
One-second
Latching
Description (Continued)
Page
Number