
7-80
Mindspeed Technologies
28229-DSH-001-B
Registers
CX28224/5/9 Data Sheet
0x416—IMA_DSL_CLOCK_GEN_ADDR (IMA DSL Clock Generator
Control)
This register is used in conjunction with 0x417 to configure the operation of the DSL
Clock Generator in the IMA core. Register 0x416 and 0x417 are an indirect register
pair in that a particular clock generator element is selected using register 0x416 and
the configuration for that element is programmed using register 0x417.
The overall operation of the clock generators are governed by the following equations:
!
Prescaler Factor = Prescaler Numerator / (Prescaler Terminal Count + 1)
!
Intermediate Frequency = Reference Clock Frequency * Prescaler Factor
!
Reference Denominator = 257 + Reference Clock Divisor
!
8 kHz = Intermediate Frequency / (Reference Denominator)
Link Payload Rate = 8 kbps * (Multiplier Factor)
A further constraint is:
!
Maximum Link Payload Rate
≤ Intermediate Frequency ≤ IMA_SysClk/16
In a typical G.shdsl application, Intermediate Frequency is set to 2.56 MHz and the
Reference Denominator is set to 320. Other settings are possible as long as the above
equations and constraints are met.
Bit
Default
Name
Description
7–5
0
Control Type
0 = Basic Setup
1 = Pre-scaler Terminal Count
2 = Pre-scaler Numerator
3 = Reference Divisor
4 = IMA Group Factor LSBs
5 = IMA Group Factor MSB
6 = Rx Timing Synthesizer Factor LSBs
7 = Rx Timing Synthesizer Factor MSB
For Control Type = 0, 1, 2, 3
4–0
——
Reserved. Set to 0.
For Control Type = 4, 5
4
0
Transmit / Receive
0 = Receive IMA Group
1 = Transmit IMA Group
3–0
0x0
Group Number
CX28224: 0–1: IMA Group 1–2
CX28225: 0–3: IMA Group 1–4
CX28229: 0–0xF: IMA Group 1–16
For Control Type = 6, 7
4–0
0x00
Port Number
CX28224: 0–1: Port 0–1
CX28225: 0–3: Port 0–3
CX28229: 0–0x1F: Port 0–31