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參數(shù)資料
| 型號(hào)： | 28229-14 |
| 廠商： | MINDSPEED TECHNOLOGIES INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PBGA256 |
| 封裝： | BGA-256 |
| 文件頁(yè)數(shù)： | 252/269頁(yè) |
| 文件大小： | 3376K |
| 代理商： | 28229-14 |
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28229-DSH-001-B
Mindspeed Technologies
5
-1
5
Transmission Convergence Block
The CX2822x’s ATM Transmission Convergence (TC) block is responsible for
recovering cell alignment using the HEC octet, performing detection/correction, and
descrambling the payload octets. The resulting ATM cells are then passed to the ATM
layer via the UTOPIA interface. Simultaneously, the ATM transmitter block is
receiving data from the ATM layer, optionally inserting header fields, optionally
calculating the HEC, and sending the cells to the framers. If no data is being received
from the ATM layer, the cell processor generates idle cells based on the data
programmed into the associated registers.
5.1
ATM Cell Transmitter
The ATM cell transmitter controls the generation and formatting of 53-octet ATM
cells that are sent to the Framer (Line) Transmit Ports. This block formats an octet
stream containing ATM data cells from the ATM layer device when those cells are
available. All 53 octets of the data cells may be obtained from the external data source
and formatted into the outgoing octet stream.
This block calculates the HEC octet in the outgoing cell from the header field. The
calculated HEC octet can be inserted in place of the incoming data octet by writing
DisHEC (bit 7) in the CGEN register (0x08) to a logic 0. For testing purposes, this
HEC octet can be corrupted by XORing the calculated value with a specific error
pattern input set in the ERRPAT register (0x0B). This HEC error is achieved by
writing ErrHEC (bit 4) in the CGEN register (0x08) to a logic 1. The remaining 48-
octet payload field of the outgoing cell is obtained from the external data source. The
payload can be scrambled.
When there is no data from the ATM layer device, the TC Block inserts idle cells
automatically in the outgoing octet stream. The 4-octet header field for these idle cells
comes from the TXIDL1–4 registers (0x14–17). The HEC octet is calculated and
inserted automatically. The payload field is filled with the octet contained in the
IDLPAY register (0x0A).
In normal operation, the 4-octet header field in the outgoing cell is passed on from the
ATM layer device. Header patterns can be modified in the TXHDR1–4 registers
(0x10–13) and inserted into outgoing cells in place of header bytes received from the
ATM layer. Whether the original header cells or replacement cells are sent is
controlled by bits 0–4 in the HDRFIELD (0x09) register.
NOTE:
When operating in the UTOPIA-to-UTOPIA mode, the ATM Cell
processor block is disabled.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 28230-13 | ATM SEGMENTATION AND REASSEMBLY DEVICE, PQFP208 |
| 28L0138-40R | 1 FUNCTIONS, FERRITE BEAD |
| 28L0138-70R | 1 FUNCTIONS, FERRITE BEAD |
| 28Z551 | TELECOM FILTER |
| 28Z550 | TELECOM FILTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28-22916 | 制造商:CEBEK 功能描述:PRE ASSEMBLED MODULE BOARD PRECISION TIMER 15S-60MIN |
| 28-22918 | 制造商:CEBEK 功能描述:PRE ASSEMBLED MODULE BOARD PRECISION TIMER 0.1-10 SEC |
| 28-22920 | 制造商:CEBEK 功能描述:PRE ASSEMBLED MODULE BOARD PRECISION TIMER 1-99 SEC |
| 28-22922 | 制造商:CEBEK 功能描述:PRE ASSEMBLED MODULE BOARD SEQUENTIAL TIMER 1SEC-3MIN |
| 28-22926 | 制造商:CEBEK 功能描述:PRE ASSEMBLED MODULE BOARD ON DELAY TIMER 1-60 SECOND |
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