
28229-DSH-001-B
Mindspeed Technologies
iv
IMA Features
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Field proven design
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All software available
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Supports variable link data rates (64K–
3.072 Mb/s)
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Internal memory
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Connects directly to the Mindspeed
SARs for inexpensive CPE solutions
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CX28224 2 ports
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CX28225 4 ports
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CX28229 32 ports
" Memory expandable to 2 M bytes via
external bus
" Up to 16 independent groups (using
external PHYs):
Each group can have up to 8 links.
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Supports IMA versions 1.0 and 1.1
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Fractional T1/E1
Cell Delineation Section
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Supports ATM cell interface for:
" Circuit-based physical layer
" Cell-based physical layer
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Performs single-bit HEC correction and
single- or multiple-bit detection
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Inserts headers and generates HEC
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Direct connection to external
Mindspeed components for:
" T1/E1
" xDSL
" General purpose mode
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Byte-level or bit-level cell delineation
Control and Status
Microprocessor Interface
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Asynchronous SRAM-like interface
mode
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Synchronous, glueless Bt8233/RS8234
SAR interface mode
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8-bit data bus
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Open-drain interrupt output
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Open-drain ready output
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8–33 MHz operation
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All control registers are read/write
UTOPIA Interfaces
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UTOPIA Level 2 Interface to ATM Layer:
" 8/16 bit operation
" 50 MHz
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PHY-side UTOPIA Interface:
" 8-bit UTOPIA Level 2
" Supports 32 ports via dual CLAV
and Enable lines
Counters/Status Register Section
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Summary interrupt indications
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Configuration of interrupt enables
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One-second counter latching
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Counters for:
" LOCD events
" Corrected HEC errors
" Uncorrected HEC errors
" Transmitted cells
" Matching received cells
" Non-matching received cells