
28229-DSH-001-B
Mindspeed Technologies
7
-81
CX28224/5/9 Data Sheet
Registers
0x417—IMA_DSL_CLOCK_GEN_DATA (IMA_DSL Clock Generator
Data)
This register is used in conjunction with 0x416 to configure the operation of the DSL
Clock Generator in the IMA core. Register 0x416 and 0x417 are an indirect register
pair in that a particular clock generator element is selected using register 0x416 and
the configuration for that element is programmed using register 0x417.
Bit
Default
Name
Description
For Control Type = 0
7
——
Reserved. Set to 0.
6
0
EnRxSyn
Enable Rx Timing Synthesizers
0 = Use SPRxClk inputs
1 = Use synthesizers instead of SPRxClk inputs
5
0
DSLClkGen
Substitute DSL clock generator
0 = Use IMA_SysClk/24 in IMA group clock and Tx_TRL selectors
1 = Use DSL Clock generator outputs when Timing Source is set to 0x20 in
register 0x411.
4
0
IMA_ClkSel
0 = Use IMA_SysClk as input to DSL Clock Generators
1 = Use IMA_RefClk as input to DSL Clock Generators
3–0
——
Reserved. Set to 0.
For Control Type = 1
7–0
0x00
Pre-scaler Terminal
Count
This field contains the terminal count of the pre-scaler clock divider. The pre-scaler
denominator is the value of this field plus 1.
For Control Type = 2
7–0
0x00
Pre-scaler Numerator This field contains the numerator for the pre-scaler.
For Control Type = 3
7–0
0x00
Reference Clock
Divisor
This field contains 8 of the 9 bits of the terminal count for the reference clock
divisor. The reference clock divisor counts from 0 to the terminal count which is
given by the value of this field plus 257. As an example if the value of this register is
63 decimal, then the reference clock divisor will be 320.
For Control Type = 4
7–0
0x00
Group Clock
Multiplier Factor
(lsbs)
This register contains the 8 lsbs of the payload bandwidth for the ports used in the
IMA group. The contents of this register are multiplied by 8kbps in order to obtain
the bandwidth.
For Control Type = 5
7–1
——
Reserved. Set to 0.
0
Group Clock
Multiplier Factor
(msb)
This register contains the msb of the payload bandwidth for the ports used in the
IMA group. The contents of this register are multiplied by 2048kbps in order to
obtain the bandwidth.
For Control Type = 6
7–0
0x00
Port Clock Multiplier
Factor (lsbs)
This register contains the 8 lsbs of the payload bandwidth for the specific port of the
Rx Timing clock synthesizer. The contents of this register are multiplied by 8kbps in
order to obtain the bandwidth.