
2-14
Mindspeed Technologies
28229-DSH-001-B
CX2822x Hardware Description
CX28224/5/9 Data Sheet
A
T
M
La
ye
r
U
T
OP
IA
Inte
rfa
ce
atmUTxClAv
ATM UTOPIA
Transmit Cell
Available
C12
O
Cell Available signal for transmit ATM cells (active high).
atmUTxSOC
ATM UTOPIA
Transmit Start of Cell
D11
I
Start of Cell synchronization signal for transmit ATM cells
(active high). Indicates that the first byte/word of the 53
byte cell is being placed on the atmUTxData bus.
atmUTxEnb*
ATM UTOPIA
Transmit Enable
B12
I
Data transfer enable for transmit ATM cells (active low).
Indicates that the first byte/word of the 53 byte cell is being
placed on the atmUTxData bus.
atmUTxClk
ATM UTOPIA
Transmit Clock
A12
I
Clock signal used for transfer of transmit ATM cells from
the ATM Layer. The maximum clock rate is 33 MHz.
atmURxSOC
ATM UTOPIA Receive
Start of Cell
C9
O
Start of Cell synchronization signal for receive ATM cells
(active high). Indicates that the first byte/word of the 53
byte cell is being placed on the atmURxData bus.
atmURxClk
ATM UTOPIA Receive
Clock
A9
I
Clock signal used for transfer of receive ATM cells from the
ATM Layer. The maximum clock rate 33 MHz.
atmURxClAv
ATM UTOPIA Receive
Cell Available
B9
O
Cell Available signal for receive ATM cells (active high). As
a software option in the IMA16 application, the pin
atmURxAdr[4] will function as a cell available status signal
(atmURxClAv[1]) for ATM Utopia addresses 8–15 only. In
this mode, atmURxClAv[1] will threestate for addresses 0–
7.
atmURxEnb*
ATM UTOPIA Receive
Enable
D8
I
Data transfer and output enable for receive ATM cells
(active low).
Table 2-3. CX2822x Pin Descriptions (9 of 12)
Pin Label
Signal Name
No.
I/O
Description