
2-24
Mindspeed Technologies
28229-DSH-001-B
CX2822x Hardware Description
CX28224/5/9 Data Sheet
M
ic
ro
In
terf
ac
e
MRdy
Microprocessor
Ready
T2
O
When active high, the current read or write transaction has
been completed. For a read transaction, the data is ready to
be transferred to the microprocessor. For a write
transaction, the data provided by the microprocessor has
been written. This pin is an open drain output for an
external wired OR logic implementation. An external pull-
up resistor is required for this pin.
MicroClk
Microprocessor
Clock
R3
I
An 8–50 MHz clock signal input. The device samples the
microprocessor interface pins (MCS*, MW/R, MAS*,
MicroAddr[10:0], and Microdata[7:0]) on the rising edge
of this signal. The microprocessor interface output pins
(Microdata[7:0], MicroInt*) are clocked on the rising edge
of MicroClk. Note that this clock is required for both
synchronous and asynchronous operations. See note in
E
xt
e
rn
al
Me
mor
y
ExtMemSel
External Memory
Enable
C13
I/PD
When this pin is pulled high, it enables the external
differential delay SRAM bus.
MemData[0]
Differential Delay
Memory Data Bus
T5
I/O/PD
Differential delay SRAM Data Bus. ATM cells extracted
from the Receive data stream are stored in the SRAM for
the purpose of differential delay compensation.
This bus is enabled by pulling the ExtMemSel pin high.
MemData[1]
P6
MemData[2]
R6
MemData[3]
N7
MemData[4]
P7
MemData[5]
N10
MemData[6]
T10
MemData[7]
R10
MemData[8]
P11
MemData[9]
N11
MemData[10]
T11
MemData[11]
R11
MemData[12]
P12
MemData[13]
N12
MemData[14]
A6
MemData[15]
B6
Table 2-5. CX28229 Pin Descriptions (3 of 12)
Pin Label
Signal Name
No.
I/O
Description