
2-8
Mindspeed Technologies
28229-DSH-001-B
CX2822x Hardware Description
CX28224/5/9 Data Sheet
M
ic
ro
In
terf
ac
e
MRdy
Microprocessor
Ready
T2
O
When active high, the current read or write transaction has
been completed. For a read transaction, the data is ready to
be transferred to the microprocessor. For a write
transaction, the data provided by the microprocessor has
been written. This pin is an open drain output for an
external wired OR logic implementation. An external pull-
up resistor is required for this pin.
MicroClk
Microprocessor
Clock
R3
I
An 8–50 MHz clock signal input. The device samples the
microprocessor interface pins (MCS*, MW/R, MRd*,
MAS*, MicroAddr[10:0], and MicroData[7:0]) on the rising
edge of this signal. The microprocessor interface output
pins (MicroData[7:0], MicroInt*) are clocked on the rising
edge of MicroClk. Note that this clock is required for both
synchronous and asynchronous operations. See note in
Ext
e
rna
lMe
mor
y
(1)
ExtMemSel
External Memory
Enable
C13
I/PD
When this pin is pulled high, it enables the external
differential delay SRAM bus. This pin is internally pulled
low on the CX28224/5.
MemData[0](1)
Differential Delay
Memory Data Bus
T5
I/O/PD
Differential delay SRAM Data Bus. ATM cells extracted
from the Receive data stream are stored in the SRAM for
the purpose of differential delay compensation.
MemData[1](1)
P6
MemData[2](1)
R6
MemData[3](1)
N7
MemData[4](1)
P7
MemData[5](1)
N10
MemData[6](1)
T10
MemData[7](1)
R10
MemData[8](1)
P11
MemData[9](1)
N11
MemData[10](1)
T11
MemData[11](1)
R11
MemData[12](1)
P12
MemData[13](1)
N12
MemData[14](1)
A6
MemData[15](1)
B6
Table 2-3. CX2822x Pin Descriptions (3 of 12)
Pin Label
Signal Name
No.
I/O
Description