
W81E381D/W81E381AD
Publication Release Date: January 2002
- 15 - Revision 0.52
4.4 USB Category
- Descriptions Summary
Mnemonic
USB Power Control SFRs
Address
Description
FPCON
Function Power Control Register
S:E7H
FPD
FRWUPE
FWKP
URDIS
URST
FRWU
FRSM
FSUS
Mnemonic
USB Interrupt System SFRs
Address
Description
FIE
USB Function Interrupt Enable
Register
S:A2H
–
–
FRXIE4
FTXIE3
FRXIE2
FTXIE1
FRXIE0
FTXIE0
FIFLG
USB
Register
Function
Interrupt
Flag
S:C0H
–
–
FRXD4
FTXD3
FRXD2
FTXD1
FRXD0
FTXD0
IEN1
USB Interrupt Enable Register
S:B1H
EA
–
–
–
EFSR
–
EF
–
Mnemonic
USB Function SFRs
Address
Description
EPCON*
Endpoint Control Register
S:E1H
RXSTL
TXSTL
CTLEP
–
RXIE
RXEPEN
TXOE
TXEPEN
EPINDEX
Endpoint Index Register
S:F1H
–
–
–
–
–
EPINX2
EPINX1
EPINX0
FADDR
Function Address Register
S:8FH
–
A6
A5
A4
A3
A2
A1
A0
RXCNT*
Receive FIFO Byte-Count Register
S:E6H
–
–
–
BC4
BC3
BC2
BC1
BC0
RXCON*
Receive FIFO Control Register
S:E4H
RXCLR
–
–
RXFFRC
RXISO
–
–
–
RXDAT*
Receive FIFO Data Register
S:E3H
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
RXFLG*
Receive FIFO Flag Register
S:E5H
–
RXFIFO
–
–
RXEMP
RXFULL
RXURF
RXOVF
RXSTAT*
Endpoint Receive Status Register
S:E2H
RXSEQ
RXSETUP
STOVW
EDOVW
RXSOVW
RXVOID
RXERR
RXACK
TXCNT*
Transmit FIFO Byte-Count Register
S:F6H
–
–
–
BC4
BC3
BC2
BC1
BC0
TXCON*
Transmit FIFO Control Register
S:F4H
TXCLR
–
–
–
–
–
–
–
TXDAT*
Transmit FIFO Data Register
S:F3H
TD7
TD6
TD5
TD4
TD3
TD2
TD1
TD0
TXFLG*
Transmit FIFO Flag Register
S:F5H
–
TXFIFO
–
–
TXEMP
TXFULL
TXURF
TXOVF
TXSTAT*
Endpoint Transmit Status Register
S:F2H
TXSEQ
–
–
TXFLUSH
TXSOVW
TXVOID
TXERR
TXACK
Mnemonic
USB Device SFRs
Address
Description
DCON
Device Control Register 1
S:B7H
TEST_MODE
SCGPIOSL
SCIOGPE
SCIOGPD
SCCLKGPE
SCCLKGPD
PTRWUEN
CONPUEN
SCON
SIE Control Register
S:BFH
SIERXDE
SIELSE
SECKPAT
STODPAT
SEOSMOD1
SEOSMOD0
SEOPMOD1
SEOPMOD0