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參數資料
| 型號： | W81E381D |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | FULL SPEED USB INTEGRATED MICROCONTROLLER |
| 中文描述： | FLASH, 12 MHz, MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48 |
| 文件頁數： | 33/63頁 |
| 文件大小： | 695K |
| 代理商： | W81E381D |
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W81E381D/W81E381AD
Publication Release Date: January 2002
- 33 - Revision 0.52
continued
Bit
Number
4
Bit
Mnemonic
EDOVW
Function
End Overwrite Flag:
This flag is set by hardware during the handshake phase of a SETUP
stage. It is set after every SETUP packet is received and must be
cleared prior to reading the contents of the FIFO. When set, the FIFO
state (RXFIF0 and read pointer) remains locked for this endpoint until
this bit is cleared. This prevents a prior, ongoing firmware read from
corrupting the read pointer after the new data has been written into the
receive FIFO. This bit is only used for control endpoints.
Note: that make sure the EDOVW bit is cleared prior to reading the
contents of the FIFO.
Receive Data Sequence Overwrite Bit:
Write ‘1’ to this bit to allow the value of the RXSEQ bit to be overwritten.
Writing a ‘0’ to this bit has no effect on RXSEQ. This bit always returns
‘0’ when read. The SIE will handle all sequence bit tracking. This bit
should be used only when initializing a new configuration or interface.
Receive Void Condition (read-only):
This bit is set when no valid data is received in response to a SETUP or
OUT token due to one of the following conditions: 1. The receive FIFO is
still locked; 2. The EPCON register's RXSTL bit is set. This bit does not
affect the F/HRXDx, RXERR or RXACK. This bit is set and cleared by
hardware. For non-isochronous transactions, this bit is updated by
hardware at the end of the transaction in response to valid OUT token.
For isochronous transactions, it is not updated until the next SOF.
Receive Error Condition (read-only):
Set when an error condition has occurred with the reception. Complete
or partial data has been written into the receive FIFO. No handshake is
returned. The error can be one of the following conditions: 1. Data failed
CRC check or bit stuffing error; 2. A receive FIFO goes into overrun of
under-run condition while receiving. The bit is updated by hardware at
the end of a valid SETUP or OUT token transaction (non-isochronous) or
at the next SOF on each valid OUT token transaction (isochronous). The
corresponding F/HRXDx bit of F/HIFLG is set when active. This bit
updated with RXACK bit at the end of data reception and is mutually
exclusive with RXACK.
Receive Acknowledged Condition (read-only):
This bit is set when data is received completely into a receive FIFO and
an ACK handshake is sent. The bit is updated by hardware at the end of
a valid SETUP or OUT token transaction (non-isochronous) or at the
next SOF on each valid OUT token transaction (isochronous). The
corresponding F/HRXDx bit of F/HIFLG is set when active. This bit
updated with RXERR bit at the end of data reception and is mutually
exclusive with RXERR.
3
RXSOVW
2
RXVOID
1
RXERR
0
RXACK
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