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參數(shù)資料
| 型號： | W81E381D |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | FULL SPEED USB INTEGRATED MICROCONTROLLER |
| 中文描述： | FLASH, 12 MHz, MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48 |
| 文件頁數(shù)： | 28/63頁 |
| 文件大小： | 695K |
| 代理商： | W81E381D |
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W81E381D/W81E381AD
Publication Release Date: January 2002
- 28 - Revision 0.52
4.5.10 Register Descriptions - USB Function SFRs (E3)
RXDAT
Address: S:E3H
Reset State: XXXX XXXXH
Receive FIFO Data Register (Endpoint-Indexed). Receive FIFO data specified by EPINDEX is stored
and read from this register.
7
6
5
4
3
2
1
0
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
Bit
Number
7
Bit
Mnemonic
RD7
Function
Receive Data Bit 7:
To write data to the receive FIFO, the FIU/HIU writes to this register. To
read data from the receive FIFO, the firmware reads from this register. The
write pointer and read pointer are incremented automatically after a write
and read, respectively.
Receive Data Bit 6:
To write data to the receive FIFO, the FIU/HIU writes to this register. To
read data from the receive FIFO, the firmware reads from this register. The
write pointer and read pointer are incremented automatically after a write
and read, respectively.
Receive Data Bit 5:
To write data to the receive FIFO, the FIU/HIU writes to this register. To
read data from the receive FIFO, the firmware reads from this register. The
write pointer and read pointer are incremented automatically after a write
and read, respectively.
Receive Data Bit 4:
To write data to the receive FIFO, the FIU/HIU writes to this register. To
read data from the receive FIFO, the firmware reads from this register. The
write pointer and read pointer are incremented automatically after a write
and read, respectively.
Receive Data Bit 3:
To write data to the receive FIFO, the FIU/HIU writes to this register. To
read data from the receive FIFO, the firmware reads from this register. The
write pointer and read pointer are incremented automatically after a write
and read, respectively.
6
RD6
5
RD5
4
RD4
3
RD3
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