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參數資料
| 型號： | W81E381D |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | FULL SPEED USB INTEGRATED MICROCONTROLLER |
| 中文描述： | FLASH, 12 MHz, MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48 |
| 文件頁數： | 58/63頁 |
| 文件大小： | 695K |
| 代理商： | W81E381D |
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W81E381D/W81E381AD
Publication Release Date: January 2002
- 58 - Revision 0.52
6. ELECTRICAL CHARACTERISTICS
Operating conditions: VCC = 4.0V to 5.25V, Ta=0
o
to 70
o
C
PARAMETER
Symbol
Conditions
Min
Max
Unit
VCC Supply Current
Icc
TBD
mA
VCC Suspend Current
Ipd
TBD
uA
Logic Output High
V
OH
I
OH
=-3mA
2.4
VCC V
Logic Output Low
V
OL
I
OL
=3mA
0.4
V
Logic Input High
V
IH
2.0
V
Logic Input Low
V
IL
Ta=70
o
C
0.8
V
Logic Input Leakage Current
10
uA
USB CHARACTERISTICS
Note 8
Leakage Current:
Hi-Z State Output Leakage
ILO
V< V IN <3.3 V
-10
+10
uA
Input Levels:
Differential Input Sensitivity
VDI
|(D+)-(D-)|
0.2
V
Single Ended Signal “0”
VSE0
0.8
2.0
V
Differential Common Mode Range
V
CM
Includes VDI range
0.8
2.5
Output Levels:
Driver Output Low
VOLU
RL of 1.5 k
to 3.6 V
0.3
V
Driver Output High
VOHU
RL of 15 k
to GND
2.8
3.6
V
Output Signal Crossover Voltage
V
CRS
1.3
2.0
V
Capacitance:
Transceiver Capacitance
CIN
Pin to GND
20
pF
Full Speed Timings:
Output Rise/Fall Times
t R /t F
Note 1, 4 (C
L
= 50 pF)
4
20
ns
Source Differential Driver Jitter to Next Transition
/ to Paired Transition
t DJ1
/tDJ2
Note 2, 3
-3.5
/-4
3.5
/4
ns
ns
Differential to EOP transition Skew
t
DEOP
Note 3
-2
5
ns
Hub Differential Data Delay(without cable)
t HDD2
Note 2,3,5
44
ns
Hub Differential Driver Jitter to Next Transition
/ to Paired Transition (including cable)
t HDJ1
/ t HDJ2
Note 2,3,5
-3
/ -1
3
/1
ns
Data bit width distortion after SOP
t SOP
Note 3,5
-5
5
ns
Hub SE0 Delay Relative to t
HDD
t EOPD
Note 3,5
0
15
ns
Hub EOP Output Width Skew
t HESK
Note 3,5
-15
15
ns
Note 1: Measured from 10% to 90% of the data signal.
Note 2: Timing difference between the differential signals.
Note 3: Measured at crossover point of differential data signals.
Note 4: The rising and falling edges should be smoothly transition (monotonic).
Note 5: Full Speed timing has a 1.5 k
pull-up to 2.8 V on the D+ (DP) data line.
Note 7: The maximum load specification is the maximum effective capacitive load allowed that meets the target hub VBUS
droop of 330 mV.
Note 8: Other USB Electrical Characteristics refer to USB spec Rev1.1 Sec7.3.2 and Sec7.3.3.
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