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參數(shù)資料
| 型號： | W81E381D |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | FULL SPEED USB INTEGRATED MICROCONTROLLER |
| 中文描述： | FLASH, 12 MHz, MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48 |
| 文件頁數(shù)： | 40/63頁 |
| 文件大小： | 695K |
| 代理商： | W81E381D |
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W81E381D/W81E381AD
Publication Release Date: January 2002
- 40 - Revision 0.52
4.5.17 Register Descriptions - USB Function SFRs (F2)
TXSTAT
Address: S:F2H
Reset State: 0XX0 0000H
Endpoint Transmit Status Register (Endpoint-Indexed). Contains the current endpoint status of the
transmit FIFO specified by EPINDEX.
7
6
5
4
3
2
1
0
TXSEQ
-
-
TXFLUSH
TXSOVW
TXVOID
TXERR
TXACK
Bit
Number
7
Bit
Mnemonic
TXSEQ
Function
Transmit Endpoint Sequence Bit (read, conditional write):
The bit will be transmitted in the next PID and toggled on a valid ACK
handshake. This bit is toggled by hardware on a valid SETUP token.
This bit can be written by firmware if the TXCOVW bit is set when written
along with the new TXSEQ value.
Reserved:
The value read from this bit is indeterminate. Write zero to this bit.
Reserved:
The value read from this bit is indeterminate. Write zero to this bit.
Transmit FIFO Packet Flushed (read-only):
When set, this bit indicates that hardware flushed a stale ISO data
packet from the transmit FIFO due to a TXFIF0=1 at SOF. To guard
against a missed IN token in ISO mode, if, with TXFIF0=1, no IN token is
received for the current endpoint, hardware automatically flushes the
oldest packet and clear TXFIF0=0.
Transmit Void Condition (read-only):
Write "1" to this bit to allow the value of the TXSEQ bit to be overwritten.
Writing "0" to this bit has no effect on TXSEQ. This bit always returns "0"
when read. This SIE will handle all sequence bit tracking. This bit should
be used only when initializing a new configuration or interface.
6
-
5
-
4
TXFLUSH
3
TXSOVW
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