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參數(shù)資料
| 型號(hào)： | W81E381D |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | FULL SPEED USB INTEGRATED MICROCONTROLLER |
| 中文描述： | FLASH, 12 MHz, MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48 |
| 文件頁數(shù)： | 21/63頁 |
| 文件大小： | 695K |
| 代理商： | W81E381D |
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W81E381D/W81E381AD
Publication Release Date: January 2002
- 21 - Revision 0.52
4.5.5
Register Descriptions - USB Function SFRs (E1)
EPCON
Address: S:E1H
Reset State(Endpoint 0): 001X 0101H
Reset State(Endpoint X): 000X 0000H
Endpoint Control Register (Endpoint-Indexed). This SFR configures the operation of the endpoint
specified by EPINDEX.
7
6
5
4
3
2
1
0
RXSTL
TXSTL
CTLEP
-
RXIE
RXEPEN
TXOE
TXEPEN
Bit
Number
7
Bit
Mnemonic
RXSTL
Function
Stall Receive Endpoint:
Set this bit to stall the receive endpoint. Clear this bit only when the host
has intervened through commands sent down endpoint 0. When this bit
is set and RXSETUP is clear, the receive endpoint will respond with a
STALL handshake to a valid OUT token. When this bit is set and
RXSETUP is set, the receive endpoint will NAK. This bit does not affect
the reception of SETUP tokens by a control endpoint.
Stall Transmit Endpoint:
Set this bit to stall the transmit endpoint. Clear this bit only when the host
has intervened through commands sent down endpoint 0. When this bit
is set and RXSETUP is clear, the receive endpoint will respond will
respond with a STALL handshake to a valid IN token. When this bit is
set and RXSETUP is set, the receive endpoint will NAK.
Control Endpoint:
Set this bit to configure the endpoint as a control endpoint. Only control
endpoints are capable of receiving SETUP tokens. For W81E381, the
endpoint 0 (EPINDEX=0000 0000) is hard-wired to "1", since endpoint 0
is always a control endpoint.
Reserved:
The value read from this bit is indeterminate. Write zero to this bit.
Receive Input Enable:
Set this bit to enable data from the USB to be written into the receive
FIFO. If cleared, the endpoint will not write the received data into the
receive FIFO at the end of reception, but will return a NAK handshake
on a valid OUT token if the RXSTL bit is not set. This bit does not affect
a valid SETUP token. A valid SETUP token and packet overrides this bit
if it is cleared, and place the receive data in the FIFO.
6
TXSTL
5
CTLEP
4
-
3
RXIE
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