
W81E381D/W81E381AD
Publication Release Date: January 2002
- 36 - Revision 0.52
4.5.15 Register Descriptions - USB Function SFRs (F3)
TXDAT
Address: S:F3H
Reset State (Other Endps): XXXX XXXXH
Reset State (Hub Endp 1): XXX0 0000H
Transmit FIFO Data Register (Endpoint-Indexed). Data to be transmitted by the FIFO specified by
EPINDEX is first written to this register.
7
6
5
4
3
2
1
0
TD7
TD6
TD5
TD4
TD3
TD2
TD1
TD0
Bit
Number
7
Bit
Mnemonic
TD7
Function
Transmit Data Bit 7:
To write data to the transmit FIFO, the firmware writes to this register. To
read data from the transmit FIFO, the Function Interface Unit reads from
this register. The write pointer and read pointer and read pointer are
incremented automatically after a write and read, respectively.
Transmit Data Bit 6:
To write data to the transmit FIFO, the firmware writes to this register. To
read data format the transmit FIFO, the Function Interface Unit reads
from this register. The write pointer and read pointer and read pointer
are incremented automatically after a write and read, respectively.
Transmit Data Bit 5:
To write data to the transmit FIFO, the firmware writes to this register. To
read data from the transmit FIFO, the Function Interface Unit reads from
this register. The write pointer and read pointer and read pointer are
incremented automatically after a write and read, respectively.
Transmit Data Bit 4:
To write data to the transmit FIFO, the firmware writes to this register. To
read data from the transmit FIFO, the Function Interface Unit reads from
this register. The write pointer and read pointer and read pointer are
incremented automatically after a write and read, respectively.
6
TD6
5
TD5
4
TD4