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參數(shù)資料
| 型號： | W81E381D |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | FULL SPEED USB INTEGRATED MICROCONTROLLER |
| 中文描述： | FLASH, 12 MHz, MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48 |
| 文件頁數(shù)： | 32/63頁 |
| 文件大小： | 695K |
| 代理商： | W81E381D |
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W81E381D/W81E381AD
Publication Release Date: January 2002
- 32 - Revision 0.52
4.5.12 Register Descriptions - USB Function SFRs (E2)
RXSTAT
Address: S:E2H
Reset State: 0000 0000
Endpoint Receive Status Register (Endpoint-Indexed). Contains the current endpoint status of the
receive FIFO specified by EPINDEX.
7
6
5
4
3
2
1
0
RXSEQ
RXSETUP
STOVW
EDOVW
RXSOVW
RXVOID
RXERR
RXACK
Bit
Number
7
Bit
Mnemonic
RXSEQ
Function
Receive Endpoint Sequence Bit(read, condition write):
The bit will be toggled on completion of an ACK handshake in response
to an OUT token. This bit will be set/cleared by hardware after reception
of a SETUP token. This bit can be written by firmware if the RXOVW bit
is set when written along with the new RXSEQ value.
Note that always verify this bit after writing to ensure that there is no
conflict with hardware, which could occurred if a new SETUP token is
received.
Received Setup Token:
This bit is set by hardware when a valid SETUP token has been
received. When set, this bit causes received IN or OUT tokens to be
“NAK”ed until the bit is cleared to allow proper data management for the
transmit and receive FIFOs from the previous transaction. IN or OUT
tokens are “NAK”ed even if the endpoint is stalled (RXSTL/TXSTL) to
allow a control transaction to clear a stalled endpoint. Clear this bit upon
detection of a SETUP token or the firmware ready to handle the
data/status stage of control transfer.
Start Overwrite Flag (read-only):
Set by hardware upon receipt of a DETUP token for any control endpoint
to indicate that the receive FIFO is being overwritten with new SETUP
data. When set, the FIFO state (RXFIFO and read pointer) resets and is
locked for this endpoint until EDOVW is set. This prevents a proper,
ongoing firmware read from corrupting the read pointer as the receive
FIFO is being cleared and new data is being written into it. This bit is
cleared by hardware at the end of handshake phase transmission of the
SETUP stage. This bit is used only for control endpoints.
6
RXSETUP
5
STOVW
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