
W81E381D/W81E381AD
Publication Release Date: January 2002
- 38 - Revision 0.52
4.5.16 Register Descriptions - USB Function SFRs (F5)
TXFLG
Address: S:F5H
Reset State: X0XX 1000H
Transmit FIFO Flag Register (Endpoint-Indexed). These flags indicate the status of data packet in the
transmit FIFO specified by EPINDEX.
7
6
5
4
3
2
1
0
-
TXFIF0
-
-
TXEMP
TXFULL
TXURF
TXOVF
Bit
Number
7
Bit
Mnemonic
-
Function
Reserved:
The value read from this bit is indeterminate. Write zero to this bit.
Transmit FIFO Index Flag (read-only):
This read-only flag indicate whether a data packet is present in the
transmit FIFO. The bit is updated after each write to TXCNT to reflect
the addition of a data packet. Likewise, the TXFIF bit is cleared in
sequence after each advance of the read marker to indicate that the set
is effectively discarded. You must check the TXFIF0 flab before and
after writes to the transmit FIFO and TXCNT for tractability. The next
state table for TXFIF0 bit is shown below in single packet mode.
TXFIF0
Operation
Flag
X
rev. RP
X
0
wr. TXCNT
X
1
wr. TXCNT
X
0
adv. RM
X
1
adv. RM
X
Reserved:
The value read from this bit is indeterminate. Write zero to this bit.
Reserved:
The value read from this bit is indeterminate. Write zero to this bit.
Transmit FIFO Empty Flag (read-only):
Hardware sets this flag when the write pointer is at the same location as
the read pointer and the write pointer equals the write marker and
neither pointer has rolled over. Hardware clears the bit when the empty
condition no longer exists. This is not a sticky bit and always tracks the
current status of the transmit FIFO, regardless of ISO or non-ISO mode.
6
TXFIF0
Next TXFIF0
Unchanged
1
1
0
0
Next Flag
Unchanged
Unchanged
TXOVF=1
TXURF=1
Unchanged
5
-
4
-
3
TXEMP