
W83977TF
PRELIMINARY
Publication Release Date:March 1998
-93 -
Revision 0.62
Table 9-2: Bit Map of GPE Register Block
Register
Address
Power-On
Reset Value
D7
D6
D5
D4
D3
D2
D1
D0
GP0STS1
<
CR62,63
>
0000 0000
0
0
MOUSCISTS
KBCSCISTS
PRTSCISTS
FDCSCISTS
URASCISTS
URBSCISTS
GP0STS2
<
CR62,63
>
+1H
0000 0000
0
0
0
0
0
0
0
0
GP0EN1
<
CR62,63
>
+2H
0000 0000
0
0
MOUSCIEN
KBCSCIEN
PRTSCIEN
FDCSCIEN
URASCIEN
URBSCIEN
GP0EN2
<
CR62,63
>
+3H
<
CR64,65
>
0000 0000
0
0
0
0
0
0
0
0
GP1STS1
0000 0000
0
0
0
0
0
0
0
BIOS_STS
GP1STS2
<
CR64,65
>
+1H
0000 0000
0
0
0
0
0
0
0
0
GP1EN1
<
CR64,65
>
+2H
0000 0000
0
0
0
0
0
0
TMR_ON
BIOS_EN
GP1EN2
<
CR64,65
>
+3H
0000 0000
0
0
0
0
0
0
BM_CNTRL
BIOS_RLS
10. SERIAL IRQ
W83977TF supports a serial IRQ scheme. This allow a signal line to be used to report the legacy ISA
interrupt rerquests. Because more than one device may need to share the signal serial IRQ signal
line, an open drain signal scheme is used. The clock source is the PCI clock. The serial interrupt is
transfered on the IRQSER signal, one cycle consisting of three frames types: a start frame, several
IRQ/Data frame, and one Stop frame.
The serial interrupt scheme adheres to the
Serial IRQ
Specification for PCI System, Version 6.0.
Timing Diagrams For IRQSER Cycle
Start Frame timing with source sampled a low pulse on IRQ1
SL
or
H
H
R
T
S
R
T
S
S
R
R
T
T
IRQ2 FRAME
IRQ1 FRAME
IRQ0 FRAME
START FRAME
START1
IRQ1
IRQ1
None
None
Host Controller
H=Host Control
SL=Slave Control
R=Recovery
T=Turn-around
S=Sample
PCICLK
IRQSER
Drive Source
1. Start Frame pulse can be 4-8 clocks wide.