
W83977TF
PRELIMINARY
Publication Release Date: March 1998
- 53 -
Revision 0.62
The contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write
operation. The leading edge of IOW
c
auses an EPP address write cycle to be performed, and the
trailing edge of IOW
latches the data for the duration of the EPP write cycle.
PD0-PD7 ports are read during a read operation. The leading edge of IOR
causes an EPP address
read cycle to be performed and the data to be output to the host CPU.
5.2.5 EPP Data Port 0-3
These four registers are available only in EPP mode. Bit definitions of each data port are as follows:
1
2
3
4
5
6
7
0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
When accesses are made to any EPP data port, the contents of DB0-DB7 are buffered (non-
inverting) and output to the ports PD0-PD7 during a write operation. The leading edge of IOW
causes
an EPP data write cycle to be performed, and the trailing edge of
IOW
latches the data for the
duration of the EPP write cycle.
During a read operation, ports PD0-PD7 are read, and the leading edge of
IOR
causes an EPP read
cycle to be performed and the data to be output to the host CPU.
5.2.6 Bit Map of Parallel Port and EPP Registers
REGISTER
7
6
5
4
3
2
1
0
Data Port (R/W)
PD7
PD6
PD
5
PD4
PD3
PD2
PD1
PD0
Status Buffer (Read)
BUSY
ACK
PE
SLCT
ERROR
1
1
TMOUT
Control Swapper (Read)
1
1
1
IRQEN
SLIN
INIT
AUTOFD
STROBE
Control Latch (Write)
1
1
DIR
IRQ
SLIN
INIT
PD2
AUTOFD
PD1
STROBE
PD0
EPP Address Port R/W)
PD7
PD6
PD
5
PD4
PD3
EPP Data Port 0 (R/W)
PD7
PD6
PD
5
PD4
PD3
PD2
PD1
PD0
EPP Data Port 1 (R/W)
PD7
PD6
PD
5
PD4
PD3
PD2
PD1
PD0