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參數資料
| 型號： | W83977TF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | Multi-Function I/O Port Controller(用于個人計算機的多功能輸入/輸出口控制器) |
| 中文描述： | 多功能I / O端口控制器（用于個人計算機的多功能輸入/輸出口控制器） |
| 文件頁數： | 90/160頁 |
| 文件大小： | 1012K |
| 代理商： | W83977TF |
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W83977TF
PRELIMINARY
Publication Release Date:March 1998
-80 -
Revision 0.62
9.3 ACPI Registers (ACPIRs)
The ACPI register model consists of the fixed register blocks that perform the ACPI functuions. A
register block may be a event register block which deals with ACPI events or a control register block
which deals with control features. The order in the event register block is a status register followed by
an enable register.
Each event register, if implemented, contains two two register: a status register and an enable
register, of 16 bits wide each. The status register indicates which event triggers the ACPI System
Control Interrupt (
SCI
). When the hardware event occurs, the corresponding status bit will be set.
However, the corresponding enable bit is also required to be set before an
SCI
interrupt could be
raised
. If the enable bit is not set, the software can examine the state of the hardware event by
reading the status bit without generating an
SCI
interrupt.
Any status bit, unless otherwise noted, can only be set by specific hardware event. It is cleared by
writing a 1 to its bit position and writing a 0 has no effect. Except some special status bits, every
status bit has the corresponding enable bit on the same bit position in the enable register. Those
status bits which have no corresponding enable bit are read for special purpose. Reverved or
unimplemented enable bits always return zero, and writing to these bits should has no effect.
The control bit in the control register provides some special control function over the hardware event,
or some special control over
SCI
event. Reserved or unimplemented control bits always return zero,
and writing to those bits should has no effect.
Table 9-1 (sec. 9.3.21)
lists the PM1 register block and its registers. The base address of PM1
register block is named as PM1a_EVT_BLK in the ACPI specification and is specified in CR60, 61 of
logical device
A
.
Table 9-2 (sec. 9.3.21)
lists the GPE register block and its registers.
The base address of general-
purpose event block GPE0 is named as GPE0_BLK in the ACPI specification and is specified in
CR62, 63 of logical device A. The base address of general-purpose event block GPE1 is named as
GPE1_BLK in the ACPI specification and is specified in CR64, 65 of logical device A.
9.3.1 Power Management 1 Status Register 1 (PM1STS1)
Register Location:
<
CR60, 61
> System I/O Space
Default Value:
00h
Attribute:
Read/write
Size:
8 bits
1
2
3
4
5
6
7
0
TMR_STS
Reserved
Reserved
Reserved
BM_STS
GBL_STS
Reserved
Reserved
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相關代理商/技術參數 |
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|---|---|
| W83977TF(EOL) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:W83877TF plus KBC. CIR. RTC |
| W83977TF_98 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:WINBOND I/O |
| W83977TF-A | 制造商:WINBOND 制造商全稱:Winbond 功能描述:I/O chip disk drive adapter |
| W83977TF-AW | 制造商:WINBOND 制造商全稱:Winbond 功能描述:WINBOND I/O |
| W83977TF-P | 制造商:WINBOND 制造商全稱:Winbond 功能描述:I/O chip disk drive adapter |
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