
W83977TF
PRELIMINARY
Publication Release Date:March 1998
-81 -
Revision 0.62
Bit
0
Name
Description
TMR_STS
This bit is the timer carry status bit. This bit is set anytime the bit 23 of the
24-bit counter changes (whenever the MSB changes from low to high or high
to low). When TMR_EN and TMR_STS are set, a power magement event is
raised. This bit is only set by hardware and can only be cleared by writing a
1 to this bit position. Writing a 0 has no effect.
Reserved.
This is the bus master status bit. Writing a 1 to BM_CNTRL also sets
BM_STS. Writing a 1 clears this bit and also clears BM_CNTRL. Writing a
0 has no effect.
This is the global status bit. This bit is set when the BIOS wants the
attention of the
SCI
handler. BIOS sets this bit by setting BIOS_RLS and
can only be cleared by writing a 1 to this bit position. Writing a 1 to this bit
position also clears BIOS_RLS. Writing a 0 has no effect.
Reserved. These bits always return zeros.
1-3
4
Reserved
BM_STS
5
GBL_STS
6-7
Reserved
9.3.2 Power Management 1 Status Register 2 (PM1STS2)
Register Location:
<
CR60, 61
> + 1H System I/O Space
Default Value:
00h
Attribute:
Read/write
Size:
8 bits
1
2
3
4
5
6
7
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
WAK_STS
Bit
Name
Description
0-6
Reserved
Reserved.
7
WAK_STS
This bit is set when the system is in the sleeping state and an enabled resume
event occurs. Upon setting this bit, the sleeping/working state machine will
transition the system to the working state. This bit is only set by hardware and
is cleared by writing a 1 to this bit position or by the sleeping/working state
machine automatically when the global standby timer expires. Writing a 0 has
no effect. When the WAK_STS is cleared and all devices are in sleeping
state, the whole chip enters the sleeping state.