
W83977TF
PRELIMINARY
Publication Release Date: April 1998
-5 -
Revision 0.62
1. PIN DESCRIPTION
Note: Please refer to Section 11.2 DC CHARACTERISTICS for details.
I/O6t - TTL level bi-directional pin with 6 mA source-sink capability
I/O8t - TTL level bi-directional pin with 8 mA source-sink capability
I/O8 - CMOS level bi-directional pin with 8 mA source-sink capability
I/O12t - TTL level bi-directional pin with 12 mA source-sink capability
I/O12 - CMOS level bi-directional pin with 12 mA source-sink capability
I/O16u - CMOS level bi-directional pin with 16 mA source-sink capability with internal pull-up resistor
I/OD16u - CMOS level bi-directional pin open drain output with 16 mA sink capability with internal pull-up resistor
I/O24t - TTL level bi-directional pin with 24 mA source-sink capability
OUT8t - TTL level output pin with 8 mA source-sink capability
OUT12t - TTL level output pin with 12 mA source-sink capability
OD12 - Open-drain output pin with 12 mA sink capability
OD24 - Open-drain output pin with 24 mA sink capability
INt - TTL level input pin
INc - CMOS level input pin
INcu - CMOS level input pin with internal pull-up resitor
INcs - CMOS level Schmitt-triggered input pin
INts - TTL level Schmitt-triggered input pin
INtsu - TTL level Schmitt-triggered input pin with internal pull-up resistor
1.1 Host Interface
SYMBOL
PIN
I/O
FUNCTION
A0
A10
A11-A14
74-84
IN
t
System address bus bits 0-10
86-89
IN
t
IN
t
I/O
12t
System address bus bits 11-14
A15
91
System address bus bit 15
D0
D5
109-
114
System data bus bits 0-5
D6
D7
116-
117
I/O
12t
System data bus bits 6-7
IOR
105
IN
ts
CPU I/O read signal
IOW
AEN
106
IN
ts
CPU I/O write signal
107
IN
ts
OD
24
System address bus enable
IOCHRDY
108
In EPP Mode, this pin is the IO Channel Ready output to extend
the host read/write cycle.
MR
118
IN
ts
Master Reset; Active high; MR is low during normal operations.