
Preliminary W6690
Publication Release Date: March 1998
- 13 -
Revision A1
The layer 1 function includes:
S/T bus transmitter/receiver
Timing recovery using digital Phase Locked Loop (DPLL) circuit
Layer 1 activation/deactivation
D channel access control
Frame alignment
Multiframe synchronization
Test functions
The serial interface bus performs the multiplexing/demultiplexing of D and 2B channels.
The B channel switching determines the connection between layer1, layer 2 and PCM.
The PCM port provides two 64 Kbps clear channels to connect to PCM codec chips.
The D channel HDLC controller performs the LAPD (Link Access Procedure on the D channel)
protocol according to ITU-T I.441/Q.921 recommendation.
There are two independent B channel HDLC controllers. They can be used to support HDLC-like
protocols such as Internet PPP.
The ISA bus Plug and Play (PNP) circuit implements the necessary Plug and Play functions if
enabled. If disabled, W6690 can interface to a ISA bus or a 8-bit micro-processor.
7.2 Layer 1 Functions Descriptions
The layer 1 functions includes :
Transmitter/Receiver which conform to the electrical specifications of ITU-T I.430
Receiver clock recovery and timing generation
Output phase delay (deviation) compensation
Layer 1 activation/deactivation procedures
D channel access control
Frame alignment
Multiframe synchronization
Test functions
7.2.1 S/T Interface Transmitter/Receiver
According to ITU-T I.430, pseudo-ternary code with 100% pulse width is used in both directions of
transmission on the S/T interface. The binary "1" is represented by no line signal (zero volt), whereas
a binary "0" is represented by a positive or negative pulse.