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參數資料
| 型號： | W6690 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ISDN S/T Interface Controller(ISDN S/T接口控制器) |
| 中文描述： | 綜合業務數字網的S / T接口控制器（綜合業務數字網S / T的接口控制器） |
| 文件頁數： | 52/76頁 |
| 文件大小： | 471K |
| 代理商： | W6690 |
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Preliminary W6690
- 52 -
8.2.1 B1_ch receive FIFO
B1_RFIFO
Read
Address 20H
The B1_RFIFO is a 64-byte depth FIFO memory with programmable threshold. The threshold value
determines when to generate an interrupt.
When more than a threshold length of data has been received, a RMR interrupt is generated. After an
RMR interrupt, 48 or 32 bytes can be read out, depending on the threshold setting.
In transparent mode, when the end of frame has been received, a RME interrupt is generated. After
an RME interrupt, the number of bytes available is less than or equal to the threshold value.
8.2.2 B1_ch transmit FIFO
B1_XFIFO
Write
Address 21H
The B1_XFIFO is a 64-byte depth FIFO with programmable threshold value. The threshold setting is
the same as B1_RFIFO.
When the number of empty locations is equal to or greater than the threshold value, a XFR interrupt
is generated. After a XFR interrupt, up to 48 or 32 bytes of data can be written into this FIFO for
transmission.
8.2.3 B1_ch command register
B1_CMDR
Write
Address 22H
Value after reset: 00H
7
6
5
4
3
2
1
0
RACK
RRST
RACT
XMS
XME
XRST
RACK Receive Message Acknowledge
After a RMR or RME interrupt, the micro-processor reads out the data in B1_RFIFO, it then sets this
bit to explicitly acknowledge the interrupt.
RRST Receiver Reset
Setting this bit resets the B1_ch HDLC receiver.
RACT Receiver Active
The B1_ch HDLC receiver is active when this bit is set to "1". This bit is write only. The receiver must
be in active state in order to receive data.
XMS Transmit Message Start/Continue
In transparent mode, setting this bit initiates the transparent transmission of B1_XFIFO data. The
opening flag is automatically added to the message by the B1_ch HDLC controller. Zero bit insertion
is performed on the data. This bit is also used in subsequent transmission of the frame.
In extended transparent mode, settint this bit activates the transmission of B1_XFIFO data. No flag,
CRC or zero bit insertion is added on the data.
XME Transmit Message End
In transparent mode, setting this bit indicates the end of the whole frame transmission. The B1_ch
HDLC controller transmits the data in FIFO and automatically appends the CRC and the closing flag
sequence in transparent mode.
In extended transparent mode, setting this bit stops the B1_XFIFO data transmission.
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