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參數(shù)資料
| 型號： | W6690 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ISDN S/T Interface Controller(ISDN S/T接口控制器) |
| 中文描述： | 綜合業(yè)務(wù)數(shù)字網(wǎng)的S / T接口控制器（綜合業(yè)務(wù)數(shù)字網(wǎng)S / T的接口控制器） |
| 文件頁數(shù)： | 17/76頁 |
| 文件大小： | 471K |
| 代理商： | W6690 |
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Preliminary W6690
Publication Release Date: March 1998
- 17 -
Revision A1
7.2.2 Receiver Clock Recovery And Timing Generation
A digital phase locked loop (DPLL) circuit is used to derive the receive clock from the received data
stream. This DPLL uses a 7.68 MHz clock as reference. According to I.430, the transmit clock is
delayed by 2 bit time from the receive clock. The "total phase deviation input to output" is -7% to
+15% of a bit period. In some cases, delay compensation may be needed to meet this requirement
(see OPS1
0 bits in D_CTL register).
Table 7.1 Output phase delay compensation table
OPS1
OPS0
EFFECT
0
0
No phase delay compensation
0
1
Phase delay compensation 260 nS
1
0
Phase delay compensation 520 nS
1
1
Phase delay compensation 1040 nS
The PCM output clocks (PFCK1-2, PBCK) are synchronous to the S-interface timing.
7.2.3 Layer 1 Activation/Deactivation
The layer 1 activation/deactivation procedures are implemented by a finite state machine. The state
transitions are triggered by signals received at S interface or commands issued from micro-processor.
The state outputs signals to S interface and indication to micro-processor. The CIX register is used by
micro-processor to issue command, and the CIR register is used by micro-processor to receive
indication.
Some commands are used for special purposes. They are "layer 1 reset", "analog loopback", "send
continuous zeros" and "send single zero".
7.2.3.1 States Descriptions And Command/Indication Codes
F3 Deactivated without clock
This is the "deactivated" state of ITU-T I.430. The receive line awake unit is active except during a
hardware reset pulse. After reset, once the indication "1111" has been read out, internal clocks will
turn off and stay at this state if INFO 0 is received on the S line. The turn off time is approximate 93
mS. The command ECK must be issued to activate the clocks.
F3 Deactivated with clock
This state is identical to "F3 Deactivated without clock" except the internal clocks are enabled. The
state is entered by a ECK command. The clocks are enabled approximately 0.5 mS to 4 mS after the
ECK command, depending on the crystal capacitances. (It is about 0.5 mS for 12 to 33 pF
capacitance).
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