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參數(shù)資料
| 型號： | W6690 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ISDN S/T Interface Controller(ISDN S/T接口控制器) |
| 中文描述： | 綜合業(yè)務(wù)數(shù)字網(wǎng)的S / T接口控制器（綜合業(yè)務(wù)數(shù)字網(wǎng)S / T的接口控制器） |
| 文件頁數(shù)： | 19/76頁 |
| 文件大?。?/td> | 471K |
| 代理商： | W6690 |
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Preliminary W6690
Publication Release Date: March 1998
- 19 -
Revision A1
A layer 1 reset command forces the transmission of INFO 0 and disables the S line awake detector.
Thus activation from NT is not possible. There is no indication in reset state. The reset state can be
left only with ECK command.
Table 7.2 Layer 1 command codes
COMMAND
SYM.
ECK
RST
SCP
SSP
AR8
CODE
0000
0001
0100
0010
1000
DESCRIPTION
Enable clock
Layer 1 reset
Send continuous pulses
Send single pulses
Activate request at priority 8
Enable internal clocks
Layer 1 reset
Send continuous pulses at 96 KHz
Send isolated pulses at 2 KHz
Activate layer 1 and set D channel priority level to
8
Activate layer 1 and set D channel priority to 10
Enable analog loopback
Deactivate layer 1 and disable internal clocks
Activate request at priority 10
Enable analog loopback
Deactivate layer 1
AR10
EAL
DRC
1001
1010
1111
Table 7.3 Layer 1 indication codes
INDICATION
SYM.
CE
DRD
CODE
0111
0000
DESCRIPTIONS
Clock Enabled
Deactivate request downstream
Internal clocks are enabled
Deactivation request by S interface, i.e INFO
0 received
Signal received, receiver not synchronous
INFO 2 received
Analog loopback activated or continuous
zeros or single zeros transmitted
Level detected during test function
INFO 4 received, D channel priority is 8 or 9
Level detected
Activate request downstream
Test indication
LD
ARD
TI
0100
1000
1010
Awake test indication
Activate indication with priority class
1
Activate indication with priority class
2
Clock disabled
ATI
AI8
1011
1100
AI10
1101
INFO 4 received, D channel priority is 10 or
11
Layer 1 deactivated, internal clocks are
disabled
CD
1111
7.2.3.2 State Transition Diagrams
The followings are the state transition diagrams which implement the activation/deactivation state
matrix in I.430 (TABLE 5/I.430). The "command" and "s receive" entries in each state octagon keeps
the state, the "indication" and "s transmit" entries in each state octagon are the state outputs. For
example, at "F3 Deactivated with clock" state, the layer 1 will stay at this state if the command is
"ECK" and the INFO 0 is received on S interface. At this state, it provides "CE" indication to the
micro-processor and transmits INFO 0 on S interface. A "AR8/10" command causes transition to F4
and non-INFO 0 signal causes transition to F5. Note that the command code writtern by the micro-
processor in CIX register and indication code written by layer 1 in CIR register are transmitted
repeatedly until a new code is written.
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